LH7A404N0F000B1A Sharp Microelectronics, LH7A404N0F000B1A Datasheet - Page 36

• Manufacturer Part Number: LH7A404N0F000B1A
• Description: IC ARM9 BLUESTREAK MCU 324CABGA
• Manufacturer: Sharp Microelectronics
• Series: BlueStreak ; LH7Ar

Specifications of LH7A404N0F000B1A

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio CODEC, EBI/EMI, IrDA, MMC, SmartCard, SSP, UART/USART, USB
• Peripherals: AC'97, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-CABGA
• For Use With: 568-4304 - BOARD EVAL FOR LH7A404
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 425-2497

LH7A404
36
A[27:0]
D[31:0]
nCS[3:0]/CS[7:6]
nWE[3:0]
nOE
SA[13:0]
A[17:16]/SB[1:0]
D[31:0]
nCAS
nRAS
nSWE
SCKE[1:0]
DQM[3:0]
nSCS[3:0]
nPCREG
D[31:0]
nPCCE1
nPCCE2
SIGNAL
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE
Input
Input
Input
NA
LOAD
50 pF
50 pF
50 pF
50 pF
30 pF
30 pF
30 pF
50 pF
50 pF
50 pF
30 pF
30 pF
30 pF
30 pF
30 pF
30 pF
30 pF
50 pF
30 pF
30 pF
ASYNCHRONOUS MEMORY INTERFACE SIGNALS (+ wait states × C)
tAS (Write)
tAS (Read)
tOVDREG
tOHDREG
SYMBOL
tOVSDW
tOHSDW
tOVCE1
tOHCE1
tOVCE2
tOHCE2
PCMCIA INTERFACE SIGNALS (+ wait states × C)
tOVDQ
SYNCHRONOUS MEMORY INTERFACE SIGNALS
tOVCA
tOHCA
tOVRA
tOHRA
tOVSC
tOHSC
tOVC0
tWHZ
tOVD
tOHD
None
tOHZ
tOVA
tOHA
tOVB
tOVD
tIHD
tIHD
tWC
tAW
tDW
tCW
tWP
tISD
tISD
tRC
tDH
tOH
tCO
tOE
tAA
Table 11. AC Signal Characteristics
2C – 10 ns
3C – 20 ns
1C – 10 ns
4C – 12 ns
3C – 20 ns
1C – 9 ns
1C + 3 ns
4C – 5 ns
4C – 5 ns
4C – 5 ns
4C – 5 ns
1.5 ns
2.5 ns
1.5 ns
4C ns
4C ns
1C ns
1C ns
MIN.
0 ns
0 ns
0 ns
2 ns
2 ns
2 ns
2 ns
2 ns
2 ns
2 ns
2 ns
2 ns
2 ns
2 ns
0
Version 1.0
1C – 10 ns
2C – 20 ns
1C - 10 ns
1C + 5 ns
1C + 5 ns
1C + 5 ns
1C + 5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
1C ns
MAX.
Read Cycle Time
Write Cycle Time
Address Valid to Write Edge
Wait State Width
Data Valid to Write Edge
Data Hold after Write Edge
Address Valid to Data Valid
Data Output Hold
Chip Select Valid to Data Valid (Read)
Chip Select Valid to Write edge
Address Valid to Chip Select Valid
(Address setup time)
Address Valid to Chip Select Valid
(Address setup time)
Write Pulse Width
Write Edge to High Z on SRAM
Output Enable Valid to Data Valid
Output Enable invalid to High Z on SRAM
Address Valid
Address Hold
Bank Select Valid
Data Valid
Data Setup
Data Hold
CAS Valid
CAS Hold
RAS Valid
RAS Hold
Write Enable Valid
Write Enable Hold
Clock Enable Valid
Data Mask Valid
Synchronous Chip Select Valid
Synchronous Chip Select Hold
nREG Valid
nREG Hold
Data Valid
Data Hold
Data Setup Time
Data Hold Time
Chip Enable 1 Valid
Chip Enable 1 Hold
Chip Enable 2 Valid
Chip Enable 2 Hold
1
1
DESCRIPTION
32-Bit System-on-Chip
Data Sheet