LH7A404N0F000B1A Sharp Microelectronics, LH7A404N0F000B1A Datasheet - Page 32

• Manufacturer Part Number: LH7A404N0F000B1A
• Description: IC ARM9 BLUESTREAK MCU 324CABGA
• Manufacturer: Sharp Microelectronics
• Series: BlueStreak ; LH7Ar

Specifications of LH7A404N0F000B1A

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio CODEC, EBI/EMI, IrDA, MMC, SmartCard, SSP, UART/USART, USB
• Peripherals: AC'97, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-CABGA
• For Use With: 568-4304 - BOARD EVAL FOR LH7A404
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 425-2497

LH7A404
Analog-To-Digital Converter
Electrical Characteristics
extended temperature operation. See Figure 6 for the
ADC transfer characteristics.
NOTES:
1. The analog section of the ADC takes 16 × A2DCLK cycles per conversion,
2. Data out = 0000000000 when the analog input equals the negative reference.
3. Guaranteed monotonic.
4. INL calculated as deviation from ‘best fit’ line after subtracting offset/gain errors over the center
5. DC voltage error for the transition voltage from code 511 (0x1FF) to 512 (0x200)
6. The internal voltage reference is driven to nominal value VREF = 2.0 V. Using the Reference Multiplexer,
7. The analog input pins can be driven anywhere between the power supply rails.
8. Bandgap and other low-bandwidth circuitry operating. All other ADC blocks shut down.
32
A/D Resolution
Throughput Conversion
Acquisition Time
Data Format
Clk Frequency
Differential Non-Linearity (DNL)
Integral Non-Linearity (INL)
Offset Error
Gain Error
Reference Voltage Output
VREF-
VREF+
Crosstalk between channels
Analog Input Voltage Range
Analog Input Current
Reference Input Current
Analog Input capacitance
Operating Supply Voltage
Operating Current, VDDA
Standby Current
Stop Current, VDDA
Brownout Trip Point (falling point)
Brownout Hysteresis
Operating Temperature
Table 8 shows the derated specifications for
plus 1 × A2DCLK cycles to be made available in the PCLK domain. An additional
3 × PCLK cycles are required before being available on the APB.
Data out = 1111111111 when the analog input equals the positive reference.
90% of full scale output range.
alternative low impedance (RS < 500) voltages can be selected as reference voltages.
The range of voltages allowed are specified above.
If the voltage at the input to the ADC exceeds VREF+ or is below VREF-, the A/D result will saturate appropriately
at positive or negative full scale. Trying to pull the analog input pins above or below the power supply rails will
cause protection diodes to be forward-biased, resulting in large current source/sink and possible damage to the ADC.
Table 8. ADC Electrical Characteristics at Industrial Operating Range
PARAMETER
(VREF+) +1.0
VSSA
-0.99
MIN.
1.85
2.36
500
-4.5
-4.0
-42
3.0
-40
10
17
3
0
binary
VSSA
VREF
TYP.
2.63
590
120
180
-60
2.0
Version 1.0
1
(VREF+) -1.0
VDDA
VDDA
MAX.
5,000
1000
+4.5
+4.5
2.15
+42
4.0
3.6
2.9
10
15
85
5
5
CLK Cycles
CLK Cycles
UNITS
LSB
LSB
LSB
Bits
mV
mV
dB
µA
µA
µA
µA
µA
ns
pF
°C
V
V
V
V
V
V
NOTES
1
32-Bit System-on-Chip
2
3
4
5
6
6
7
8
Data Sheet