ST7FMC2S6TC STMicroelectronics, ST7FMC2S6TC Datasheet - Page 88

IC MCU 8BIT 32K FLASH 44-LQFP

ST7FMC2S6TC

Manufacturer Part Number
ST7FMC2S6TC
Description
IC MCU 8BIT 32K FLASH 44-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST7FMC2S6TC

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
LINSCI, SPI
Peripherals
LVD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
44-LQFP
For Use With
497-8402 - BOARD EVAL COMPLETE INVERTER497-8400 - KIT IGBT PWR MODULE CTRL ST7MC497-6408 - BOARD EVAL BLDC SENSORLESS MOTOR497-4734 - EVAL KIT 3KW POWER DRIVER BOARD497-4733 - EVAL KIT 1KW POWER DRIVER BOARD497-4732 - EVAL KIT 300W POWER DRIVER BOARD497-4731 - EVAL KIT PWR DRIVER CONTROL BRD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST7FMC2S6TC
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
ST7FMC2S6TCE
Manufacturer:
STMicroelectronics
Quantity:
10 000
ST7MC1xx/ST7MC2xx
16-BIT TIMER
10.3.4 Low Power Modes
10.3.5 Interrupts
Note:
10.3.6 Summary of Timer modes
3)
1
Wait
Halt
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
Input Capture (1 and/or 2)
Output Compare (1 and/or 2)
One Pulse Mode
PWM Mode
See note 4 in
No effect on 16-bit Timer.
Timer interrupts cause the Device to exit from Wait mode.
16-bit Timer registers are frozen.
In Halt mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count
when the Device is woken up by an interrupt with “exit from Halt mode” capability or from the counter reset
value when the Device is woken up by a RESET.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-
ly, when the Device is woken up by an interrupt with “exit from Halt mode” capability, the ICFi bit is set, and
the counter value present when exiting from Halt mode is captured into the ICiR register.
Section 10.3.3.6 Pulse Width Modulation Mode
Yes
Yes
No
No
Not Recommended
Not Recommended
Yes
Yes
1)
3)
OCF1
OCF2
ICF1
ICF2
TOF
Yes
Yes
No
No
OCIE
TOIE
ICIE
Yes
Yes
Yes
Yes
Yes
Partially
Yes
Yes
No
No
No
No
No
No
2)

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