Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 161

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
18.6 Error Detection
18.6.1 Transmit Overrun
18.6.2 Mode Fault (Multi-Master Collision)
18.6.3 Slave Mode Abort
18.6.4 Receive Overrun
18.7 SPI Interrupts
DS0200-003
SPI contains error detection logic to recognize when communication errors have occurred. If SPI_CTL.IRQE
is set to ‘1’, one or more of the error conditions asserting generates an interrupt. SPI_STAT indicates which
error has been detected. Writing a ‘1’ to these bits in SPI_STAT clears the interrupt condition.
A transmit overrun error indicates that a write to the SPI Data register was attempted when the internal
transmit FIFO was full in either Master or Slave modes. An overrun sets SPI_STAT.TOVR to ‘1’.
A mode fault indicates when more than one Master is trying to communicate at the same time (a multi-
master collision). The mode fault is detected when an enabled Master’s nSS input pin is asserted low. A
mode fault sets SPI_STAT.COL to ‘1’.
In Slave mode of operation, if the nSS pin de-asserts before all bits in a character have been transferred, the
transaction is aborted. When this condition occurs, the ABT bit is set in the SPI_STA. The next time nSS
asserts, the MISO pin outputs SPI_DAT[15], regardless of where the previous transaction left off. Writing 1
to ABT bit clears this error flag.
A receive overrun error indicates a write to the receive FIFO occurred when the internal receive FIFO was
full (in either Master or Slave modes). An overrun sets the ROVR bit in the SPI Status register to 1. Writing 1
to ROVR bit clears this error flag.
When SPI_CTL.IRQE is set, SPI generates an interrupt when one of the following interrupt conditions
occurs:
The interrupt condition is indicated in SPI_STAT.IRQ.



A data interrupt occurs when the transmit character has been fully moved out of the shift
register and the Transmit FIFO is empty (in either Master or Slave mode). Since transmit and
receive are always interlocked, there is no need for a separate receive interrupt.
If either SPI_DMA.RXDMA or SPI_DMA.TDMA is set, the data interrupt is not asserted,
however error interrupts will still occur. To start the data transfer process, an SPI interrupt can
be forced by software writing SPI_CTL.STR to ‘1’.
If any of error conditions occur, the corresponding error bit and IRQ are set in SPI_STAT and
an interrupt is asserted. The error status bits and IRQ must be cleared at the same time by
writing 1 to those bits.
If SPI is disabled, an interrupt can be generated by a Baud Rate Generator time-out. This timer
function must be enabled by setting SPI_CTL.BIRQ to ‘1’.
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