IC MCU 4MHZ 1.2K OTP 20-SOIC

MC68HC705J1ACDW

Manufacturer Part NumberMC68HC705J1ACDW
DescriptionIC MCU 4MHZ 1.2K OTP 20-SOIC
ManufacturerFreescale Semiconductor
SeriesHC05
MC68HC705J1ACDW datasheet
 


Specifications of MC68HC705J1ACDW

Core ProcessorHC05Core Size8-Bit
Speed4MHzPeripheralsPOR, WDT
Number Of I /o14Program Memory Size1.2KB (1.2K x 8)
Program Memory TypeOTPRam Size64 x 8
Voltage - Supply (vcc/vdd)3 V ~ 5.5 VOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case20-SOIC (7.5mm Width)
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantEeprom Size-
Data Converters-Connectivity-
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Freescale Semiconductor
MC68HC705J1A
MC68HRC705J1A
MC68HSC705J1A
MC68HSR705J1A
Technical Data
M68HC05
Microcontrollers
MC68HC705J1A/D
Rev. 4, 5/2002
© Freescale Semiconductor, Inc., 2004. All rights reserved.
For More Information On This Product,
Go to: www.freescale.com

MC68HC705J1ACDW Summary of contents

  • Page 1

    ... Freescale Semiconductor Microcontrollers © Freescale Semiconductor, Inc., 2004. All rights reserved. M68HC05 For More Information On This Product, Go to: www.freescale.com MC68HC705J1A MC68HRC705J1A MC68HSC705J1A MC68HSR705J1A Technical Data MC68HC705J1A/D Rev. 4, 5/2002 ...

  • Page 2

    ... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...

  • Page 3

    ... Freescale Semiconductor, Inc. MC68HC705J1A MC68HRC705J1A MC68HSC705J1A MC68HSR705J1A Technical Data To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www ...

  • Page 4

    ... Freescale Semiconductor, Inc. Technical Data Revision Date Level Figure 2-2. I/O Register Summary last entry (Mask Option Register) Figure 2-4. Mask Option Register (MOR) May, 2002 4.0 state 6.3.3 Pulldown Register A 6.4.3 Pulldown Register B Technical Data Revision History Description — Corrected reset state for — ...

  • Page 5

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705J1A Section 1. General Description . . . . . . . . . . . . . . . . . . . . 21 Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Section 3. Central Processor Unit (CPU Section 4. Resets and Interrupts . . . . . . . . . . . . . . . . . . . 69 Section 5. Low-Power Modes Section 6. Parallel Input/Output (I/O) Ports . . . . . . . . . . 87 Section 7. Computer Operating Properly Section 8. External Interrupt Module (IRQ 101 Section 9. Multifunction Timer Module . . . . . . . . . . . . . 109 Section 10 ...

  • Page 6

    ... Freescale Semiconductor, Inc. List of Sections Technical Data List of Sections For More Information On This Product, Go to: www.freescale.com MC68HC705J1A — Rev. 4.0 ...

  • Page 7

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705J1A 1.1 1.2 1.3 1.4 1.5 1.5.1 1.5.2 1.5.2.1 1.5.2.2 1.5.2.3 1.5.2.4 1.6 1.7 1.8 1.9 2.1 2.2 2.3 2.4 2.5 MC68HC705J1A — Rev. 4.0 For More Information On This Product, Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Features ...

  • Page 8

    ... Freescale Semiconductor, Inc. Table of Contents 2.6 2.6.1 2.6.2 2.6.3 2.7 2.8 3.1 3.2 3.3 3.4 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 3.6 3.6.1 3.6.1.1 3.6.1.2 3.6.1.3 3.6.1.4 3.6.1.5 3.6.1.6 3.6.1.7 3.6.1.8 3.6.2 3.6.2.1 3.6.2.2 3.6.2.3 3.6.2.4 3.6.2.5 Technical Data EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 EPROM/OTPROM Programming . . . . . . . . . . . . . . . . . . . . . 38 EPROM Programming Register ...

  • Page 9

    ... Freescale Semiconductor, Inc. 3.7 3.8 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.4 4.4.1 4.4.2 4.4.3 4.4.3.1 4.4.3.2 4.4.4 5.1 5.2 5.3 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.5 MC68HC705J1A — Rev. 4.0 For More Information On This Product, Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Opcode Map ...

  • Page 10

    ... Freescale Semiconductor, Inc. Table of Contents 6.1 6.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.4 6.4.1 6.4.2 6.4.3 6.5 6.6 7.1 7.2 7.3 7.3.1 7.3.2 7.3.3 7.4 7.5 7.6 7.6.1 7.6.2 Technical Data Section 6. Parallel Input/Output (I/O) Ports Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Port Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Data Direction Register A ...

  • Page 11

    ... Freescale Semiconductor, Inc. 8.1 8.2 8.3 8.3.1 8.3.2 8.4 8.5 8.5.1 8.5.2 9.1 9.2 9.3 9.4 9.5 9.5.1 9.5.2 9.6 9.6.1 9.6.2 10.1 10.2 10.3 10.4 10.5 MC68HC705J1A — Rev. 4.0 For More Information On This Product, Section 8. External Interrupt Module (IRQ) Contents ...

  • Page 12

    ... Freescale Semiconductor, Inc. Table of Contents 10.6 10.7 10.8 10.9 10.10 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.11 EPROM Programming Characteristics . . . . . . . . . . . . . . . . . . 126 10.12 5.0-Volt Control Timing 10.13 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 11.1 11.2 11.3 11.4 11.5 12.1 12.2 12.3 A.1 A.2 A.3 A.4 A.5 Technical Data Power Considerations ...

  • Page 13

    ... Freescale Semiconductor, Inc. B.1 B.2 B.3 B.4 B.5 B.6 C.1 C.2 C.3 C.4 C.5 C.6 C.7 MC68HC705J1A — Rev. 4.0 For More Information On This Product, Appendix B. MC68HSC705J1A Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 5.0-Volt DC Electrical Characteristics .142 3.3-Volt DC Electrical Characteristics .142 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Package Types and Order Numbers ...

  • Page 14

    ... Freescale Semiconductor, Inc. Table of Contents Technical Data Table of Contents For More Information On This Product, Go to: www.freescale.com MC68HC705J1A — Rev. 4.0 ...

  • Page 15

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705J1A Figure 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 2-1 2-2 2-3 2-4 3-1 3-2 3-3 3-4 3-5 3-6 4-1 4-2 MC68HC705J1A — Rev. 4.0 For More Information On This Product, Title Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Pin Assignments .26 Bypassing Layout Recommendation ...

  • Page 16

    ... Freescale Semiconductor, Inc. List of Figures Figure 4-3 4-4 4-5 4-6 4-7 5-1 5-2 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 7-1 8-1 8-2 8-3 8-4 9-1 9-2 9-3 9-4 Technical Data Title External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 External Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Interrupt Stacking Order ...

  • Page 17

    ... Freescale Semiconductor, Inc. Figure 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 A-1 A-2 B-1 B-2 C-1 C-2 C-3 MC68HC705J1A — Rev. 4.0 For More Information On This Product, Title PA0–PA7, PB0–PB5 Typical High-Side Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 123 PA0–PA3, PB0–PB5 Typical Low-Side Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 123 PA4– ...

  • Page 18

    ... Freescale Semiconductor, Inc. List of Figures Technical Data List of Figures For More Information On This Product, Go to: www.freescale.com MC68HC705J1A — Rev. 4.0 ...

  • Page 19

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705J1A Table 1-1 3-1 3-2 3-3 3-4 3-5 3-6 3-7 4-1 4-2 4-3 4-4 6-1 6-2 9-1 12-1 A-1 B-1 C-1 MC68HC705J1A — Rev. 4.0 For More Information On This Product, Title Programmable Options Register/Memory Instructions Read-Modify-Write Instructions ...

  • Page 20

    ... Freescale Semiconductor, Inc. List of Tables Technical Data List of Tables For More Information On This Product, Go to: www.freescale.com MC68HC705J1A — Rev. 4.0 ...

  • Page 21

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705J1A 1.1 Contents 1.2 1.3 1.4 1.5 1.5.1 1.5.2 1.5.2.1 1.5.2.2 1.5.2.3 1.5.2.4 1.6 1.7 1.8 1.9 MC68HC705J1A — Rev. 4.0 For More Information On This Product, Section 1. General Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Programmable Options Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 ...

  • Page 22

    ... Freescale Semiconductor, Inc. General Description 1.2 Introduction The MC68HC705J1A is a member of Motorola’s low-cost, high-performance M68HC05 Family of 8-bit microcontroller units (MCUs). The M68HC05 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the popular M68HC05 central processor unit (CPU) and are available with a variety of subsystems, memory sizes and types, and package types ...

  • Page 23

    ... Freescale Semiconductor, Inc. OSC1 INTERNAL OSCILLATOR OSC2 RESET IRQ/V PP MC68HC705J1A — Rev. 4.0 For More Information On This Product, 15-STAGE DIVIDE MULTIFUNCTION BY ³2 TIMER SYSTEM WATCHDOG AND ILLEGAL ADDRESS DETECT CPU CONTROL ALU 68HC05 CPU ACCUMULATOR CPU REGISTERS INDEX REGISTER STK PTR ...

  • Page 24

    ... Freescale Semiconductor, Inc. General Description 1.3 Features Features of the MC68HC705J1A include: • • • • • • • • • • • • Technical Data Peripheral modules: – 15-stage multifunction timer – Computer operating properly (COP) watchdog 14 bidirectional input/output (I/O) lines, including: – ...

  • Page 25

    ... Freescale Semiconductor, Inc. 1.4 Programmable Options The options in (MOR). COP watchdog timer External interrupt triggering Port A IRQ pin interrupts Port pulldown resistors STOP instruction mode Crystal oscillator internal resistor EPROM security Short oscillator delay counter 1.5 Pin Assignments Figure 1-2 1.5.1 V ...

  • Page 26

    ... Freescale Semiconductor, Inc. General Description Technical Data OSC1 1 OSC2 2 PB5 3 PB4 4 PB3 5 PB2 6 PB1 7 PB0 Figure 1-2. Pin Assignments MCU C2 0 Figure 1-3. Bypassing Layout Recommendation General Description For More Information On This Product, Go to: www.freescale.com 20 RESET 19 IRQ PA0 17 PA1 16 PA2 15 PA3 ...

  • Page 27

    ... Freescale Semiconductor, Inc. 1.5.2 OSC1 and OSC2 The OSC1 and OSC2 pins are the connections for the on-chip oscillator. The oscillator can be driven by any of these: 1. Crystal (See 2. Ceramic resonator (See 3. Resistor/capacitor (RC) oscillator (Refer to 4. External clock signal (See The frequency two to produce the internal operating frequency ...

  • Page 28

    ... Freescale Semiconductor, Inc. General Description 1.5.2.2 Ceramic Resonator Oscillator To reduce cost, use a ceramic resonator instead of the crystal. The circuits shown in circuits. Follow the resonator manufacturer’s recommendations, as the resonator parameters determine the external component values required for maximum stability and reliable starting. The load capacitance values used in the oscillator circuit design should include all stray capacitances ...

  • Page 29

    ... Freescale Semiconductor, Inc. Mount the resonator and components as close as possible to the pins for startup stabilization and to minimize output distortion. An internal startup resistor of approximately provided between OSC1 and OSC2 as a programmable mask option MC68HC705J1A — Rev. 4.0 For More Information On This Product, ...

  • Page 30

    ... Freescale Semiconductor, Inc. General Description 1.5.2.3 RC Oscillator Refer to MC68HSR705J1A. 1.5.2.4 External Clock An external clock from another complementary metal-oxide semiconductor (CMOS)-compatible device can be connected to the OSC1 input, with the OSC2 input not connected, as shown in Figure crystal/ceramic resonator or the RC oscillator is enabled. 1.6 RESET Applying a logic 0 to the RESET pin forces the MCU to a known startup state ...

  • Page 31

    ... Freescale Semiconductor, Inc. 1.7 IRQ/V PP The external interrupt/programming voltage pin (IRQ/V asynchronous IRQ interrupt function of the CPU. Additionally used to program the user EPROM and mask option register. (See Memory The LEVEL bit in the mask option register provides negative edge-sensitive triggering or both negative edge-sensitive and low level-sensitive triggering for the interrupt function ...

  • Page 32

    ... Freescale Semiconductor, Inc. General Description Technical Data General Description For More Information On This Product, Go to: www.freescale.com MC68HC705J1A — Rev. 4.0 ...

  • Page 33

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705J1A 2.1 Contents 2.2 2.3 2.4 2.5 2.6 2.6.1 2.6.2 2.6.3 2.7 2.8 2.2 Introduction This section describes the organization of the on-chip memory consisting of: • • MC68HC705J1A — Rev. 4.0 For More Information On This Product, Introduction ...

  • Page 34

    ... Freescale Semiconductor, Inc. Memory 2.3 Memory Map $0000 I/O Registers 32 Bytes $001F $0020 Unimplemented 160 Bytes $00BF $00C0 RAM 64 Bytes $00FF $0100 Unimplemented 512 Bytes $02FF $0300 EPROM 1232 Bytes $07CF $07D0 Unimplemented 30 Bytes $07ED $07EE Test ROM 2 Bytes $07EF $07F0 ...

  • Page 35

    ... Freescale Semiconductor, Inc. 2.4 Input/Output Register Summary Addr. Register Name Read: Port A Data Register $0000 (PORTA) Write: See page 89. Reset: Read: Port B Data Register $0001 (PORTB) Write: See page 92. Reset: $0002 Unimplemented $0003 Unimplemented Read: Data Direction Register A $0004 (DDRA) Write: See page 90 ...

  • Page 36

    ... Freescale Semiconductor, Inc. Memory Addr. Register Name Read: Timer Counter Register $0009 (TCR) Write: See page 114. Reset: Read: IRQ Status and Control $000A Register (ISCR) Write: See page 106. Reset: $000B Unimplemented $000F Unimplemented Read: Pulldown Register A $0010 (PDRA) Write: See page 91 ...

  • Page 37

    ... Freescale Semiconductor, Inc. Addr. Register Name $0019 Unimplemented $001E Unimplemented $001F Reserved Read: COP Register $07F0 (COPR) Write: See page 99. Reset: Read: Mask Option Register $07F1 (MOR) Write: See page 41. Reset: Figure 2-2. I/O Register Summary (Sheet 2.5 RAM The 64 addresses from $00C0 to $00FF serve as both the user RAM and the stack RAM ...

  • Page 38

    ... Freescale Semiconductor, Inc. Memory 2.6 EPROM/OTPROM A microcontroller unit (MCU) with a quartz window has 1240 bytes of erasable, programmable ROM (EPROM). The quartz window allows EPROM erasure with ultraviolet light. NOTE: Keep the quartz window covered with an opaque material except when programming the MCU. Ambient light can affect MCU operation. ...

  • Page 39

    ... Freescale Semiconductor, Inc. 2.6.2 EPROM Programming Register The EPROM programming register (EPROG) contains the control bits for programming the EPROM/OTPROM. Address: Read: Write: Reset: ELAT — EPROM Bus Latch Bit This read/write bit latches the address and data buses for EPROM/OTPROM programming. Clearing the ELAT bit automatically clears the EPGM bit ...

  • Page 40

    ... Freescale Semiconductor, Inc. Memory NOTE: Writing logic 1s to both the ELAT and EPGM bits with a single instruction sets ELAT and clears EPGM. ELAT must be set first by a separate instruction. Bits [7:3] — Reserved Take these steps to program a byte of EPROM/OTPROM: 1. Apply the programming voltage ...

  • Page 41

    ... Freescale Semiconductor, Inc. Take these steps to program the mask option register: 1. Apply the programming voltage Write to the MOR. 3. Set the MPGM bit and wait for a time Clear the MPGM bit. 5. Reset the MCU. Address: Read: Write: Reset: SOSCD — Short Oscillator Delay Bit The SOSCD bit controls the oscillator stabilization counter ...

  • Page 42

    ... Freescale Semiconductor, Inc. Memory SWAIT — Stop-to-Wait Conversion Bit The SWAIT bit enables halt mode. When the SWAIT bit is set, the CPU interprets the STOP instruction as a WAIT instruction, and the MCU enters halt mode. Halt mode is the same as wait mode, except that an oscillator stabilization delay 4064 t exiting halt mode ...

  • Page 43

    ... Freescale Semiconductor, Inc. 2.8 EPROM Programming Characteristics Programming voltage IRQ/V Programming current IRQ/V Programming time Per array byte MOR MC68HC705J1A — Rev. 4.0 For More Information On This Product, (1) Symbol Characteristic EPGM t MPGM = 5.0 Vdc 10 Vdc – +105 Memory Go to: www.freescale.com Memory ...

  • Page 44

    ... Freescale Semiconductor, Inc. Memory Technical Data Memory For More Information On This Product, Go to: www.freescale.com MC68HC705J1A — Rev. 4.0 ...

  • Page 45

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705J1A Section 3. Central Processor Unit (CPU) 3.1 Contents 3.2 3.3 3.4 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 3.6 3.6.1 3.6.1.1 3.6.1.2 3.6.1.3 3.6.1.4 3.6.1.5 3.6.1.6 3.6.1.7 3.6.1.8 3.6.2 3.6.2.1 3.6.2.2 3.6.2.3 3.6.2.4 3.6.2.5 3.7 3.8 MC68HC705J1A — ...

  • Page 46

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 3.2 Introduction The central processor unit (CPU) consists of a CPU control unit, an arithmetic/logic unit (ALU), and five CPU registers. The CPU control unit fetches and decodes instructions. The ALU executes the instructions. The CPU registers contain data, addresses, and status bits that reflect the results of CPU operations ...

  • Page 47

    ... Freescale Semiconductor, Inc. CPU CONTROL UNIT HALF-CARRY FLAG CARRY/BORROW FLAG MC68HC705J1A — Rev. 4.0 For More Information On This Product, ARITHMETIC/LOGIC UNIT INTERRUPT MASK NEGATIVE FLAG ZERO FLAG Figure 3-1. Programming Model Central Processor Unit (CPU) Go to: www.freescale.com Central Processor Unit (CPU) ...

  • Page 48

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 3.5 CPU Registers The M68HC05 CPU contains five registers that control and monitor microcontroller unit (MCU) operation: • • • • • CPU registers are not memory mapped. 3.5.1 Accumulator The accumulator ( general-purpose 8-bit register. The CPU uses the accumulator to hold operands and results of ALU operations ...

  • Page 49

    ... Freescale Semiconductor, Inc. 3.5.3 Stack Pointer The stack pointer (SP 16-bit register that contains the address of the next location on the stack. During a reset or after the reset stack pointer instruction (RSP), the stack pointer is preset to $00FF. The address in the stack pointer decrements after a byte is stacked and increments before a byte is unstacked ...

  • Page 50

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 3.5.4 Program Counter The program counter (PC 16-bit register that contains the address of the next instruction or operand to be fetched. The five most significant bits of the program counter are ignored and appear as 00000. Normally, the address in the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched ...

  • Page 51

    ... Freescale Semiconductor, Inc. H — Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between bits 3 and 4 of the accumulator during an ADD (add without carry) or ADC (add with carry) operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations. ...

  • Page 52

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 3.6 Instruction Set The MCU instruction set has 62 instructions and uses eight addressing modes. 3.6.1 Addressing Modes The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes provide eight different ways for the CPU to find the data required to execute an instruction ...

  • Page 53

    ... Freescale Semiconductor, Inc. 3.6.1.3 Direct Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address. ...

  • Page 54

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) The k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. 3.6.1.7 Indexed, 16-Bit Offset Indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode ...

  • Page 55

    ... Freescale Semiconductor, Inc. 3.6.2 Instruction Types The MCU instructions fall into these five categories: • • • • • 3.6.2.1 Register/Memory Instructions These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. MC68HC705J1A — ...

  • Page 56

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 3.6.2.2 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. NOTE: Do not use read-modify-write instructions on registers with write-only bits. ...

  • Page 57

    ... Freescale Semiconductor, Inc. 3.6.2.3 Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met ...

  • Page 58

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Technical Data Table 3-3. Jump and Branch Instructions Instruction Branch if carry bit clear Branch if carry bit set Branch if equal Branch if half-carry bit clear Branch if half-carry bit set Branch if higher Branch if higher or same Branch if IRQ pin high ...

  • Page 59

    ... Freescale Semiconductor, Inc. 3.6.2.4 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations ...

  • Page 60

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 3.6.2.5 Control Instructions These instructions act on CPU registers and control CPU operation during program execution. Technical Data Table 3-5. Control Instructions Instruction Clear carry bit Clear interrupt mask No operation Reset stack pointer Return from interrupt ...

  • Page 61

    ... Freescale Semiconductor, Inc. 3.7 Instruction Set Summary Table 3-6. Instruction Set Summary (Sheet Source Operation Form ADC #opr ADC opr ADC opr Add with Carry ADC opr,X ADC opr,X ADC ,X ADD #opr ADD opr ADD opr Add without Carry ADD opr,X ...

  • Page 62

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Table 3-6. Instruction Set Summary (Sheet Source Operation Form BHI rel Branch if Higher BHS rel Branch if Higher or Same BIH rel Branch if IRQ Pin High BIL rel Branch if IRQ Pin Low BIT #opr BIT opr ...

  • Page 63

    ... Freescale Semiconductor, Inc. Table 3-6. Instruction Set Summary (Sheet Source Operation Form BSR rel Branch to Subroutine CLC Clear Carry Bit CLI Clear Interrupt Mask CLR opr CLRA CLRX Clear Byte CLR opr,X CLR ,X CMP #opr CMP opr CMP opr Compare Accumulator with Memory Byte ...

  • Page 64

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Table 3-6. Instruction Set Summary (Sheet Source Operation Form JMP opr JMP opr JMP opr,X Unconditional Jump JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X Jump to Subroutine JSR opr,X JSR ,X LDA #opr LDA opr ...

  • Page 65

    ... Freescale Semiconductor, Inc. Table 3-6. Instruction Set Summary (Sheet Source Operation Form ROL opr ROLA ROLX Rotate Byte Left through Carry Bit ROL opr,X ROL ,X ROR opr RORA RORX Rotate Byte Right through Carry Bit ROR opr,X ROR ,X RSP Reset Stack Pointer ...

  • Page 66

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Table 3-6. Instruction Set Summary (Sheet Source Operation Form SWI Software Interrupt TAX Transfer Accumulator to Index Register TST opr TSTA TSTX Test Memory Byte for Negative or Zero TST opr,X TST ,X TXA Transfer Index Register to Accumulator ...

  • Page 67

    ... Freescale Semiconductor, Inc. MC68HC705J1A — Rev. 4.0 For More Information On This Product, Central Processor Unit (CPU) Go to: www.freescale.com Central Processor Unit (CPU) Opcode Map Technical Data ...

  • Page 68

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Technical Data Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com MC68HC705J1A — Rev. 4.0 ...

  • Page 69

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705J1A 4.1 Contents 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.4 4.4.1 4.4.2 4.4.3 4.4.3.1 4.4.3.2 4.4.4 4.2 Introduction Reset initializes the microcontroller unit (MCU) by returning the program counter to a known address and by forcing control and status bits to known states ...

  • Page 70

    ... Freescale Semiconductor, Inc. Resets and Interrupts 4.3 Resets A reset immediately stops the operation of the instruction being executed, initializes certain control and status bits, and loads the program counter with a user-defined reset vector address. These sources can generate a reset: • • • ...

  • Page 71

    ... Freescale Semiconductor, Inc. 4.3.1 Power-On Reset A positive transition on the V NOTE: The power-on reset is strictly for power-up conditions and cannot be used to detect drops in power supply voltage. A 4064-t active allows the clock generator to stabilize. If any reset source is active at the end of this delay, the MCU remains in the reset condition until all reset sources are inactive ...

  • Page 72

    ... Freescale Semiconductor, Inc. Resets and Interrupts 4.3.2 External Reset A logic 0 applied to the RESET pin for 1 1/2 t reset. A Schmitt trigger senses the logic level at the RESET pin. INTERNAL INTERNAL ADDRESS BUS INTERNAL DATA BUS Notes: 1. Internal clock, internal address bus, and internal data bus are not available externally. ...

  • Page 73

    ... Freescale Semiconductor, Inc. 4.4 Interrupts These sources can generate interrupts: • • • An interrupt temporarily stops the program sequence to process a particular event. An interrupt does not stop the operation of the instruction being executed, but takes effect when the current instruction completes its execution. Interrupt processing automatically saves the CPU registers on the stack and loads the program counter with a user-defined interrupt vector address ...

  • Page 74

    ... Freescale Semiconductor, Inc. Resets and Interrupts The CPU clears the IRQ latch during interrupt processing, so that another interrupt signal on the IRQ/V request during the interrupt service routine. As soon as the I bit is cleared during the return from interrupt, the CPU can recognize the new interrupt request ...

  • Page 75

    ... Freescale Semiconductor, Inc. IRQ PIN IRQ IRQ n IRQ (INTERNAL) Figure 4-5. External Interrupt Timing Interrupt pulse width low (edge-triggered) Interrupt pulse period The minimum, t plus 19 Interrupt pulse width low (edge-triggered) Interrupt pulse period The minimum, t plus 19 MC68HC705J1A — Rev. 4.0 For More Information On This Product, ...

  • Page 76

    ... Freescale Semiconductor, Inc. Resets and Interrupts 4.4.3 Timer Interrupts The timer can generate these interrupt requests: • • Setting the I bit in the condition code register disables timer interrupts. 4.4.3.1 Real-Time Interrupt A real-time interrupt occurs if the real-time interrupt flag, RTIF, becomes set while the real-time interrupt enable bit, RTIE, is also set. RTIF and RTIE are in the timer status and control register ...

  • Page 77

    ... Freescale Semiconductor, Inc STACKING ORDER Function Reset Software interrupt (SWI) External interrupt Timer interrupts 1. The COP watchdog is programmable in the mask option register. MC68HC705J1A — Rev. 4.0 For More Information On This Product, • UNSTACKING ORDER • • 1 CONDITION CODE REGISTER 2 ACCUMULATOR 3 INDEX REGISTER ...

  • Page 78

    ... Freescale Semiconductor, Inc. Resets and Interrupts Technical Data FROM RESET YES I BIT SET? NO YES EXTERNAL INTERRUPT? NO TIMER YES INTERRUPT? NO LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI YES INSTRUCTION? NO RTI YES INSTRUCTION? NO Figure 4-7. Interrupt Flowchart Resets and Interrupts For More Information On This Product, Go to: www ...

  • Page 79

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705J1A 5.1 Contents 5.2 5.3 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.5 5.2 Introduction The microcontroller unit (MCU) can enter these low-power standby modes: • • • MC68HC705J1A — Rev. 4.0 For More Information On This Product, Section 5 ...

  • Page 80

    ... Freescale Semiconductor, Inc. Low-Power Modes • 5.3 Exiting Stop and Wait Modes The events described in this subsection bring the MCU out of stop mode and load the program counter with the reset vector or with an interrupt vector. Exiting stop mode: • • Exiting wait mode: • ...

  • Page 81

    ... Freescale Semiconductor, Inc. • • 5.4 Effects of Stop and Wait Modes The STOP and WAIT instructions have the effects described in this subsection on MCU modules. 5.4.1 Clock Generation The STOP instruction: The STOP instruction disables the internal oscillator, stopping the CPU clock and all peripheral clocks. ...

  • Page 82

    ... Freescale Semiconductor, Inc. Low-Power Modes 5.4.2 CPU The STOP instruction: • • After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay. After exit from stop mode by external interrupt, the I bit remains clear. After exit from stop mode by reset, the I bit is set. ...

  • Page 83

    ... Freescale Semiconductor, Inc. After exit from stop mode by reset: • • The WAIT instruction: The WAIT instruction has no effect on the COP watchdog. NOTE: To prevent a COP timeout during wait mode, exit wait mode periodically to service the COP. 5.4.4 Timer The STOP instruction: • ...

  • Page 84

    ... Freescale Semiconductor, Inc. Low-Power Modes 5.4.5 EPROM/OTPROM The STOP instruction: The STOP instruction during erasable, programmable read-only memory (EPROM) programming clears the EPGM bit in the EPROM programming register, removing the programming voltage from the EPROM. The WAIT instruction: The WAIT instruction has no effect on EPROM/one-time programmable read-only memory (OTPROM) operation ...

  • Page 85

    ... Freescale Semiconductor, Inc. 5.5 Timing OSC (NOTE RESET t ILIH IRQ/V PP (NOTE 2) IRQ/V PP (NOTE 3) INTERNAL CLOCK INTERNAL ADDRESS BUS Notes: 1. Internal clocking from OSC1 pin 2. Edge-triggered external interrupt mask option 3. Edge- and level-triggered external interrupt mask option 4. Reset vector shown as example Figure 5-1. Stop Mode Recovery Timing MC68HC705J1A — ...

  • Page 86

    ... Freescale Semiconductor, Inc. Low-Power Modes STOP SWAIT BIT SET? NO CLEAR I BIT IN CCR SET IRQE BIT IN ISCR CLEAR TOF, RTIF, TOIE, AND RTIE BITS IN TSCR TURN OFF INTERNAL OSCILLATOR YES EXTERNAL RESET? NO YES EXTERNAL INTERRUPT? NO TURN ON INTERNAL OSCILLATOR RESET STABILIZATION TIMER END OF ...

  • Page 87

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705J1A Section 6. Parallel Input/Output (I/O) Ports 6.1 Contents 6.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.4 6.4.1 6.4.2 6.4.3 6.5 6.6 6.2 Introduction Fourteen bidirectional pins form one 8-bit input/output (I/O) port and one 6-bit I/O port. All the bidirectional port pins are programmable as inputs or outputs ...

  • Page 88

    ... Freescale Semiconductor, Inc. Parallel Input/Output (I/O) Ports Addr. Register Name Read: Port A Data Register $0000 (PORTA) Write: See page 89. Reset: Read: Port B Data Register $0001 (PORTB) Write: See page 92. Reset: Read: Data Direction Register A $0004 (DDRA) Write: See page 90. Reset: Read: ...

  • Page 89

    ... Freescale Semiconductor, Inc. 6.3 Port A Port 8-bit bidirectional port. 6.3.1 Port A Data Register The port A data register (PORTA) contains a latch for each port A pin. Address: Read: Write: Reset: PA[7:0] — Port A Data Bits These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A ...

  • Page 90

    ... Freescale Semiconductor, Inc. Parallel Input/Output (I/O) Ports 6.3.2 Data Direction Register A Data direction register A (DDRA) determines whether each port A pin is an input or an output. Address: Read: Write: Reset: DDRA[7:0] — Data Direction Register A Bits These read/write bits control port A data direction. Reset clears DDRA[7:0], configuring all port A pins as inputs ...

  • Page 91

    ... Freescale Semiconductor, Inc. Writing a logic DDRA bit enables the output buffer for the corresponding port A pin; a logic 0 disables the output buffer. When bit DDRAx is a logic 1, reading address $0000 reads the PAx data latch. When bit DDRAx is a logic 0, reading address $0000 reads the voltage level on the pin ...

  • Page 92

    ... Freescale Semiconductor, Inc. Parallel Input/Output (I/O) Ports 6.3.4 Port A LED Drive Capability The outputs for the upper four bits of port A (PA4–PA7) can drive light-emitting diodes (LEDs). PA4–PA7 can sink approximately current to V 6.3.5 Port A I/O Pin Interrupts If the PIRQ bit in the mask option register is programmed to logic 1, PA0– ...

  • Page 93

    ... Freescale Semiconductor, Inc. 6.4.2 Data Direction Register B Data direction register B (DDRB) determines whether each port B pin is an input or an output. Address: Read: Write: Reset: DDRB[5:0] — Data Direction Register B Bits These read/write bits control port B data direction. Reset clears DDRB[5:0], configuring all port B pins as inputs. ...

  • Page 94

    ... Freescale Semiconductor, Inc. Parallel Input/Output (I/O) Ports Writing a logic DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the output buffer. When bit DDRBx is a logic 1, reading address $0001 reads the PBx data latch. When bit DDRBx is a logic 0, reading address $0001 reads the voltage level on the pin ...

  • Page 95

    ... Freescale Semiconductor, Inc. 6.5 5.0-Volt I/O Port Electrical Characteristics Characteristic Current drain per pin excluding PA4–PA7 Output high voltage (I = 0.8 mA) PA0–PA7, PB0–PB5 – Load Output low voltage (I = 1.6 mA) PA0–PA3, PB0–PB5 Load (I = 10.0 mA) PA4–PA7 Load Input high voltage PA0– ...

  • Page 96

    ... Freescale Semiconductor, Inc. Parallel Input/Output (I/O) Ports Technical Data Parallel Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com MC68HC705J1A — Rev. 4.0 ...

  • Page 97

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705J1A Section 7. Computer Operating Properly (COP) Module 7.1 Contents 7.2 7.3 7.3.1 7.3.2 7.3.3 7.4 7.5 7.6 7.6.1 7.6.2 7.2 Introduction The computer operating properly (COP) watchdog resets the microcontroller (MCU) in case of software failure. Software that is operating properly periodically services the COP watchdog and prevents COP reset ...

  • Page 98

    ... Freescale Semiconductor, Inc. Computer Operating Properly (COP) Module 7.3 Operation Operation of the COP is described in this subsection. 7.3.1 COP Watchdog Timeout Four counter stages at the end of the timer make up the COP watchdog. The COP resets the MCU if the timeout period occurs before the COP ...

  • Page 99

    ... Freescale Semiconductor, Inc. Clearing the COP bit disables the COP watchdog timer regardless of the IRQ/V If the main program executes within the COP timeout period, the clearing routine should be executed only once. If the main program takes longer than the COP timeout period, the clearing routine must be executed more than once ...

  • Page 100

    ... Freescale Semiconductor, Inc. Computer Operating Properly (COP) Module 7.6 Low-Power Modes The STOP and WAIT instructions have these effects on the COP watchdog. 7.6.1 Stop Mode The STOP instruction clears the COP watchdog counter and disables the clock to the COP watchdog. NOTE: ...

  • Page 101

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705J1A Section 8. External Interrupt Module (IRQ) 8.1 Contents 8.2 8.3 8.3.1 8.3.2 8.4 8.5 8.5.1 8.5.2 8.2 Introduction The external interrupt (IRQ) module provides asynchronous external interrupts to the CPU. These sources can generate external interrupts: • ...

  • Page 102

    ... Freescale Semiconductor, Inc. External Interrupt Module (IRQ) 8.3 Operation The interrupt request/programming voltage pin (IRQ/V pins 0–3 (PA0–PA3) provide external interrupts. The PIRQ bit in the mask option register (MOR) enables PA0–PA3 as IRQ interrupt sources, which are combined into a single ORing function to be latched by the IRQ latch ...

  • Page 103

    ... Freescale Semiconductor, Inc. MC68HC705J1A — Rev. 4.0 For More Information On This Product, FROM RESET YES I BIT SET? NO YES EXTERNAL INTERRUPT? NO TIMER YES INTERRUPT? STACK PCL, PCH CCR NO LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI YES INSTRUCTION? NO RTI YES INSTRUCTION? UNSTACK CCR PCH, PCL ...

  • Page 104

    ... Freescale Semiconductor, Inc. External Interrupt Module (IRQ) 8.3.1 IRQ/V Pin PP An interrupt signal on the IRQ/V request. The LEVEL bit in the mask option register provides negative edge-sensitive triggering or both negative edge-sensitive and low level-sensitive triggering for the interrupt function. If edge- and level-sensitive triggering is selected, a falling edge or a low ...

  • Page 105

    ... Freescale Semiconductor, Inc. If edge- and level-sensitive triggering is selected, a rising edge or a high level on a PA0–PA3 pin latches an external interrupt request. Edge- and level-sensitive triggering allows the use of multiple wired-OR external interrupt sources. As long as any source is holding a PA0–PA3 pin high, an external interrupt request is latched, and the CPU continues to execute the interrupt service routine ...

  • Page 106

    ... Freescale Semiconductor, Inc. External Interrupt Module (IRQ) 8.4 IRQ Status and Control Register The IRQ status and control register (ISCR) controls and monitors operation of the IRQ module. All unused bits in the ISCR read as logic 0s. The IRQF bit is cleared and the IRQE bit is set by reset. ...

  • Page 107

    ... Freescale Semiconductor, Inc. 8.5 External Interrupt Timing IRQ PIN IRQ IRQ n IRQ (INTERNAL) Figure 8-4. External Interrupt Timing 8.5.1 5.0-Volt External Interrupt Timing Characteristics Characteristic IRQ interrupt pulse width low (edge-triggered) IRQ interrupt pulse width (edge- and level-triggered) PA0–PA3 interrupt pulse width high (edge-triggered) PA0– ...

  • Page 108

    ... Freescale Semiconductor, Inc. External Interrupt Module (IRQ) Technical Data External Interrupt Module (IRQ) For More Information On This Product, Go to: www.freescale.com MC68HC705J1A — Rev. 4.0 ...

  • Page 109

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705J1A 9.1 Contents 9.2 9.3 9.4 9.5 9.5.1 9.5.2 9.6 9.6.1 9.6.2 9.2 Introduction The multifunction timer provides a timing reference with programmable real-time interrupt (RTI) capability. organization. Features include: • • • MC68HC705J1A — Rev. 4.0 For More Information On This Product, Section 9 ...

  • Page 110

    ... Freescale Semiconductor, Inc. Multifunction Timer Module OVERFLOW RESET Figure 9-1. Multifunction Timer Block Diagram Technical Data TIMER COUNTER REGISTER BITS [0:7] OF 15-STAGE RIPPLE COUNTER RESET TIMER STATUS/CONTROL REGISTER RTI RATE SELECT BITS [8:14] OF 15-STAGE RIPPLE COUNTER 8 Multifunction Timer Module For More Information On This Product, Go to: www ...

  • Page 111

    ... Freescale Semiconductor, Inc. Addr. Register Name Read: Timer Status and Control $0008 Register (TSCR) Write: See page 112. Reset: Read: Timer Counter Register (TCR) $0009 Write: See page 114. Reset: 9.3 Operation A 15-stage ripple counter, preceded by a prescaler that divides the internal clock signal by four, provides the timing reference for the timer functions ...

  • Page 112

    ... Freescale Semiconductor, Inc. Multifunction Timer Module 9.4 Interrupts These timer sources can generate interrupts: • • 9.5 I/O Registers These registers control and monitor the timer operation: • • 9.5.1 Timer Status and Control Register The read/write timer status and control register (TSCR) performs these functions: • ...

  • Page 113

    ... Freescale Semiconductor, Inc. TOF — Timer Overflow Flag This read-only flag becomes set when the first eight stages of the counter roll over from $FF to $00. TOF generates a timer overflow interrupt request if TOIE is also set. Clear TOF by writing a logic 1 to the TOFR bit. Writing to TOF has no effect. Reset clears TOF. ...

  • Page 114

    ... Freescale Semiconductor, Inc. Multifunction Timer Module interrupt request to be generated. To prevent this occurrence, clear the COP timer before changing RT1 and RT0. RT1:RT0 1. At 2-MHz bus, 4-MHz XTAL, 0.5 s per cycle 9.5.2 Timer Counter Register A 15-stage ripple counter is the core of the timer. The value of the first ...

  • Page 115

    ... Freescale Semiconductor, Inc. 9.6 Low-Power Modes The STOP and WAIT instructions put the MCU in low power-consumption standby states. 9.6.1 Stop Mode The STOP instruction has these effects on the timer: • • 9.6.2 Wait Mode The timer remains active after a WAIT instruction. Any enabled timer interrupt request can bring the MCU out of wait mode. MC68HC705J1A — ...

  • Page 116

    ... Freescale Semiconductor, Inc. Multifunction Timer Module Technical Data Multifunction Timer Module For More Information On This Product, Go to: www.freescale.com MC68HC705J1A — Rev. 4.0 ...

  • Page 117

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705J1A 10.1 Contents 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.11 EPROM Programming Characteristics . . . . . . . . . . . . . . . . . . 126 10.12 5.0-Volt Control Timing 10.13 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 10.2 Introduction This section contains electrical and timing specifications. ...

  • Page 118

    ... Freescale Semiconductor, Inc. Electrical Specifications 10.3 Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table here ...

  • Page 119

    ... Freescale Semiconductor, Inc. 10.4 Operating Temperature Range MC68HC705J1AP MC68HC705J1AC MC68HC705J1AV plastic dual in-line package (PDIP small outline integrated circuit (SOIC ceramic DIP (cerdip extended temperature range automotive temperature range 10.5 Thermal Characteristics Thermal resistance MC68HC705J1AP MC68HC705J1ADW MC68HC705J1AS plastic dual in-line package (PDIP) 2 ...

  • Page 120

    ... Freescale Semiconductor, Inc. Electrical Specifications 10.6 Power Considerations The average chip junction temperature, T Where For most applications, P Ignoring P Solving equations (1) and (2) for K gives: where constant pertaining to the particular part. K can be determined from equation (3) by measuring P known T by solving equations (1) and (2) iteratively for any value of T ...

  • Page 121

    ... Freescale Semiconductor, Inc. 10.7 5.0-Volt DC Electrical Characteristics Characteristic Output voltage I = 10.0 A Load I = –10.0 A Load Output high voltage (I = –0.8 mA) PA0–PA7, PB0–PB5 Load Output low voltage (I = 1.6 mA) PA0–PA3, PB0–PB5 Load (I = 10.0 mA) PA4–PA7 Load Input high voltage PA0–PA7, PB0–PB5, IRQ/V ...

  • Page 122

    ... Freescale Semiconductor, Inc. Electrical Specifications 10.8 3.3-Volt DC Electrical Characteristics Characteristic Output voltage I = 10.0 A Load I = –10.0 A Load Output high voltage (I = –0.2 mA) PA0–PA7, PB0–PB5 Load Output low voltage (I = 0.4 mA) PA0–PA3, PB0–PB5 Load (I = 5.0 mA) PA4–PA7 Load Input high voltage PA0– ...

  • Page 123

    ... Freescale Semiconductor, Inc. 10.9 Driver Characteristics 800 mV 700 mV 600 mV 500 mV 400 mV 300 mV 200 mV 100 1.0 mA 2.0 mA 3 Notes 5.0 V, devices are specified and tested for ( 3.3 V, devices are specified and tested for (V DD Figure 10-1. PA0–PA7, PB0–PB5 Typical High-Side Driver Characteristics ...

  • Page 124

    ... Freescale Semiconductor, Inc. Electrical Specifications 800 mV 700 mV 600 mV 500 mV 400 mV 300 mV 200 mV 100 Notes 5.0 V, devices are specified and tested for 3.3 V, devices are specified and tested for V DD Figure 10-3. PA4–PA7 Typical Low-Side Driver Characteristics Technical Data 800 mV 700 mV ...

  • Page 125

    ... Freescale Semiconductor, Inc. 10.10 Typical Supply Currents Notes Notes MC68HC705J1A — Rev. 4.0 For More Information On This Product, 6.0 mA 5.0 mA 4.0 mA 3.0 mA 2.0 mA 3.6 V 1 1.0 MHz INTERNAL OPERATING FREQUENCY (f = 5.0 V, devices are specified and tested for 3.3 V, devices are specified and tested for I DD Figure 10-4 ...

  • Page 126

    ... Freescale Semiconductor, Inc. Electrical Specifications 10.11 EPROM Programming Characteristics Characteristic Programming voltage IRQ/V PP Programming current IRQ/V PP Programming time Per array byte MOR 5.0 Vdc 10 Vdc 10.12 5.0-Volt Control Timing Characteristic Oscillator frequency Crystal oscillator option External clock source Internal operating frequency (f ...

  • Page 127

    ... Freescale Semiconductor, Inc. 10.13 3.3-Volt Control Timing Characteristic Oscillator frequency Crystal oscillator option External clock source Internal operating frequency (f osc Crystal oscillator External clock Cycle time ( RESET pulse width low IRQ interrupt pulse width low (edge-triggered) IRQ interrupt pulse width low (edge- and level-triggered) PA0– ...

  • Page 128

    ... Freescale Semiconductor, Inc. Electrical Specifications IRQ PIN IRQ IRQ n IRQ (INTERNAL) Figure 10-6. External Interrupt Timing OSC (NOTE RESET t ILIH IRQ (NOTE 2) IRQ (NOTE 3) INTERNAL CLOCK INTERNAL ADDRESS BUS Notes : 1. Internal clocking from OSC1 pin 2. Edge-triggered external interrupt mask option 3. Edge- and level-triggered external interrupt mask option 4 ...

  • Page 129

    ... Freescale Semiconductor, Inc (NOTE 1) OSC1 PIN INTERNAL CLOCK INTERNAL ADDRESS BUS INTERNAL DATA BUS Notes : 1. Power-on reset threshold is typically between 1 V and Internal clock, internal address bus, and internal data bus are not available externally. Figure 10-8. Power-On Reset Timing INTERNAL ...

  • Page 130

    ... Freescale Semiconductor, Inc. Electrical Specifications Technical Data Electrical Specifications For More Information On This Product, Go to: www.freescale.com MC68HC705J1A — Rev. 4.0 ...

  • Page 131

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705J1A 11.1 Contents 11.2 11.3 11.4 11.5 11.2 Introduction The MC68HC705J1A, the resistor-capacitor (RC) oscillator, and high-speed option devices described in MC68HRC705J1A, MC68HSR705J1A • • • MC68HC705J1A — Rev. 4.0 For More Information On This Product, Section 11. Mechanical Specifications Introduction ...

  • Page 132

    ... Freescale Semiconductor, Inc. Mechanical Specifications 11.3 Plastic Dual In-Line Package (Case 738) - -T- SEATING PLANE 11.4 Small Outline Integrated Circuit (Case 751 0.010 (0.25 Technical Data 0.25 (0.010 0.25 (0.010 0.010 (0.25 -T- M SEATING PLANE K Mechanical Specifications For More Information On This Product, Go to: www ...

  • Page 133

    ... Freescale Semiconductor, Inc. 11.5 Ceramic Dual In-Line Package (Case 732 SEATING PLANE MC68HC705J1A — Rev. 4.0 For More Information On This Product, Ceramic Dual In-Line Package (Case 732 Mechanical Specifications Go to: www.freescale.com Mechanical Specifications NOTES: 1. LEADS WITHIN 0.010 DIAMETER, TRUE POSITION AT SEATING PLANE, AT MAXIMUM MATERIAL CONDITION ...

  • Page 134

    ... Freescale Semiconductor, Inc. Mechanical Specifications Technical Data Mechanical Specifications For More Information On This Product, Go to: www.freescale.com MC68HC705J1A — Rev. 4.0 ...

  • Page 135

    ... 751D-04 20 –40 to +85 C –40 to +105 732-03 20 –40 to +85 C –40 to +105 C Appendix A. MC68HRC705J1A, Appendix B. for ordering information on optional high-speed and Go to: www.freescale.com Section 11. (1) Order Number (2) MC68HC705J1AP (3) MC68HC705J1AC P (4) MC68HC705J1AV P (5) MC68HC705J1ADW MC68HC705J1ACDW MC68HC705J1AVDW (6) MC68HC705J1AS MC68HC705J1ACS MC68HC705J1AVS MC68HSC705J1A, and Technical Data ...

  • Page 136

    ... Freescale Semiconductor, Inc. Ordering Information Technical Data Ordering Information For More Information On This Product, Go to: www.freescale.com MC68HC705J1A — Rev. 4.0 ...

  • Page 137

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705J1A A.1 Contents A.2 A.3 A.4 A.5 A.2 Introduction This appendix introduces the MC68HRC705J1A, a resistor-capacitor (RC) oscillator mask option version of the MC68HC705J1A. All of the information in this document applies to the MC68HRC705J1A with the exceptions given in this appendix. ...

  • Page 138

    ... Freescale Semiconductor, Inc. MC68HRC705J1A A.3 RC Oscillator Connections For greater cost reduction, the RC oscillator mask option allows the configuration shown in the RC components as close as possible to the pins for startup stabilization and to minimize output distortion. NOTE: The optional internal resistor is not recommended for configurations that ...

  • Page 139

    ... Freescale Semiconductor, Inc. A.4 Typical Internal Operating Frequency for RC Oscillator Option Figure A-2 RC oscillator option. NOTE: Tolerance for resistance is 50%. When selecting resistor size, consider the tolerance to ensure that the resulting oscillator frequency does not exceed the maximum operating frequency 0.1 ...

  • Page 140

    ... Freescale Semiconductor, Inc. MC68HRC705J1A A.5 Package Types and Order Numbers Package Type PDIP SOIC Cerdip 1. Refer plastic dual in-line package (PDIP extended temperature range automotive temperature range small outline integrated circuit (SOIC ceramic dual in-line package (cerdip) Technical Data Table A-1. MC68HRC705J1A (RC Oscillator Option) ...

  • Page 141

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705J1A B.1 Contents B.2 B.3 B.4 B.5 B.6 B.2 Introduction This appendix introduces the MC68HSC705J1A, a high-speed version of the MC68HC705J1A. All of the information in this document applies to the MC68HSC705J1A with the exceptions given in this appendix. MC68HC705J1A — Rev. 4.0 For More Information On This Product, Appendix B ...

  • Page 142

    ... Freescale Semiconductor, Inc. MC68HSC705J1A B.3 5.0-Volt DC Electrical Characteristics Supply current (f Run Wait B.4 3.3-Volt DC Electrical Characteristics Supply current (f Run Wait B.5 Typical Supply Currents Technical Data Characteristic = 4.0 MHz) OP Characteristic = 2.1 MHz) OP 7.0 mA 6.0 mA 5.0 mA SEE NOTE 2 4.0 mA 3.0 mA 2.0 mA 1.0 mA ...

  • Page 143

    ... Freescale Semiconductor, Inc. MC68HC705J1A — Rev. 4.0 For More Information On This Product, 700 A 600 A 500 A 400 A 300 A 200 A 100 1.0 MHz 2.0 MHz INTERNAL OPERATING FREQUENCY (f Notes 5.0 V, high-speed devices are specified and tested for 4.0 MHz 3.3 V, high-speed devices are specified and tested for ...

  • Page 144

    ... Freescale Semiconductor, Inc. MC68HSC705J1A B.6 Package Types and Order Numbers Package Type PDIP SOIC Cerdip 1. Refer plastic dual in-line package (PDIP extended temperature range small outline integrated circuit (SOIC ceramic dual in-line package (cerdip) Technical Data Table B-1. MC68HSC705J1A (High Speed) Order Numbers ...

  • Page 145

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705J1A C.1 Contents C.2 C.3 C.4 C.5 C.6 C.7 C.2 Introduction This appendix introduces the MC68HSR705J1A, a high-speed version of the MC68HRC705J1A. All of the information in this document applies to the MC68HSR705J1A with the exceptions given in this appendix. C.3 RC Oscillator Connections (External Resistor) Refer to resistor-capacitor (RC) oscillator connections with external resistor ...

  • Page 146

    ... Freescale Semiconductor, Inc. MC68HSR705J1A C.4 Typical Internal Operating Frequency for High-Speed RC Oscillator Option For lower frequency operation characteristics, refer to MC68HRC705J1A. NOTE: Tolerance for resistance is 50 percent. When selecting resistor size, consider the tolerance to ensure that resulting oscillator frequency does not exceed the maximum operating frequency. ...

  • Page 147

    ... Freescale Semiconductor, Inc. C.5 RC Oscillator Connections (No External Resistor) For maximum cost reduction, the RC oscillator mask connections shown in Figure C-2 components. This can be accomplished by programming the oscillator internal resistor (OSCRES) bit in the mask option register to a logic 1. When programming the OSCRES bit for the MC68HSR705J1A, an ...

  • Page 148

    ... Freescale Semiconductor, Inc. MC68HSR705J1A C.6 Typical Internal Operating Frequency versus Temperature (No External Resistor) 3.00 2.50 2.00 1.50 1.00 0.50 0.00 –50 0 Figure C-3. Typical Internal Operating Frequency versus Temperature (OSCRES Bit = 1) NOTE: Due to process variations, operating voltages, and temperature requirements, the internal resistance and tolerance are unspecified. ...

  • Page 149

    ... Freescale Semiconductor, Inc. C.7 Package Types and Order Numbers Package Type PDIP SOIC Cerdip 1. Refer plastic dual in-line package (PDIP extended temperature range small outline integrated circuit (SOIC ceramic dual in-line package (cerdip) MC68HC705J1A — Rev. 4.0 For More Information On This Product, ...

  • Page 150

    ... Freescale Semiconductor, Inc. MC68HSR705J1A Technical Data MC68HSR705J1A For More Information On This Product, Go to: www.freescale.com MC68HC705J1A — Rev. 4.0 ...

  • Page 151

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705J1A accumulator register ( addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . brownout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . central processor unit (CPU computer operating properly (COP) module . . . . . . . . . . . . . . . . . . . condition code register (CCR COP watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 152

    ... Freescale Semiconductor, Inc. Index CPU registers accumulator register (A index register ( program counter register (PC stack pointer register (SP data direction registers data direction register A (DDRA data direction register B (DDRB data-retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 153

    ... Freescale Semiconductor, Inc. external interrupt module (IRQ external interrupt pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . external reset general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I bit index register ( instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 154

    ... Freescale Semiconductor, Inc. Index real-time interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset/interrupt vector addresses software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . software interrupt vector sources timer interrupt vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76, timer overflow IRQ latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 155

    ... Freescale Semiconductor, Inc. mask option register (MOR programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC68HC705J1A features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC68HRC705J1A (RC oscillator option operating frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RC oscillator connections MC68HSC705J1A (high-speed option electrical characteristics order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 156

    ... Freescale Semiconductor, Inc. Index opcode map options (mask options (programmable ordering information MC68HRC705J1A (RC oscillator option MC68HSC705J1A (high-speed option MC68HSR705J1A (high-speed RC oscillator option order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . 135, 140, 144, OSC1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 157

    ... Freescale Semiconductor, Inc. I/O circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pins port B data register (PORTB pulldown register (PDRB power dissipation power-on reset program counter (PC programmable options programming model (CPU pulldown register A (PDRA pulldown register B (PDRB pulldown resistors programmable option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 158

    ... Freescale Semiconductor, Inc. Index RTIE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTIF bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTIFR bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Schmitt trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31, 104, SOSCD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . stack pointer register (SP STOP instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81, 100, stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82, effect on COP watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . effects on timer STOP instruction flowchart stop recovery timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 159

    ... Freescale Semiconductor, Inc. V pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DD V pin WAIT instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81, 100, wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . effects on timer bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC68HC705J1A — Rev. 4.0 For More Information On This Product Index Go to: www.freescale.com Index 25 25 106 100 115 51 Technical Data ...

  • Page 160

    ... Freescale Semiconductor, Inc. Index Technical Data Index For More Information On This Product, Go to: www.freescale.com MC68HC705J1A — Rev. 4.0 ...

  • Page 161

    ... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...

  • Page 162

    ... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...