IC MCU 4MHZ 1.2K OTP 20-SOIC

MC68HC705J1ACDW

Manufacturer Part NumberMC68HC705J1ACDW
DescriptionIC MCU 4MHZ 1.2K OTP 20-SOIC
ManufacturerFreescale Semiconductor
SeriesHC05
MC68HC705J1ACDW datasheet
 


Specifications of MC68HC705J1ACDW

Core ProcessorHC05Core Size8-Bit
Speed4MHzPeripheralsPOR, WDT
Number Of I /o14Program Memory Size1.2KB (1.2K x 8)
Program Memory TypeOTPRam Size64 x 8
Voltage - Supply (vcc/vdd)3 V ~ 5.5 VOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case20-SOIC (7.5mm Width)
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantEeprom Size-
Data Converters-Connectivity-
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Freescale Semiconductor, Inc.
Computer Operating Properly (COP) Module
7.3 Operation
Operation of the COP is described in this subsection.
7.3.1 COP Watchdog Timeout
Four counter stages at the end of the timer make up the COP watchdog.
The COP resets the MCU if the timeout period occurs before the COP
watchdog timer is cleared by application software and the IRQ/V
voltage is between V
a new timeout period and prevents COP reset. A COP watchdog timeout
indicates that the software is not executing instructions in the correct
sequence.
NOTE:
The internal clock drives the COP watchdog. Therefore, the COP
watchdog cannot generate a reset for errors that cause the internal clock
to stop.
The COP watchdog depends on a power supply voltage at or above a
minimum specification and is not guaranteed to protect against
brownout.
7.3.2 COP Watchdog Timeout Period
The COP watchdog timer function is implemented by dividing the output
of the real-time interrupt circuit (RTI) by eight. The RTI select bits in the
timer status and control register control RTI output, and the selected
output drives the COP watchdog. See timer status and control register
in
Section 9. Multifunction Timer
NOTE:
The minimum COP timeout period is seven times the RTI period. The
COP is cleared asynchronously with the value in the RTI divider; hence,
the COP timeout period will vary between 7x and 8x the RTI period.
7.3.3 Clearing the COP Watchdog
To clear the COP watchdog and prevent a COP reset, write a logic 0 to
bit 0 (COPC) of the COP register at location $07F0 (see
Technical Data
and V
. Periodically clearing the counter starts
SS
DD
Computer Operating Properly (COP) Module
For More Information On This Product,
Go to: www.freescale.com
PP
Module.
Figure
7-1).
MC68HC705J1A — Rev. 4.0
pin