MC68HC705J1ACDW Freescale Semiconductor, MC68HC705J1ACDW Datasheet - Page 81
Manufacturer Part Number
IC MCU 4MHZ 1.2K OTP 20-SOIC
Specifications of MC68HC705J1ACDW
Number Of I /o
Program Memory Size
1.2KB (1.2K x 8)
Program Memory Type
64 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
5.4 Effects of Stop and Wait Modes
5.4.1 Clock Generation
MC68HC705J1A — Rev. 4.0
The STOP and WAIT instructions have the effects described in this
subsection on MCU modules.
The STOP instruction:
The oscillator stabilization delay holds the MCU in reset for the first 4064
internal clock cycles.
The WAIT instruction:
The STOP instruction disables the internal oscillator, stopping the
CPU clock and all peripheral clocks.
After exiting stop mode, the CPU clock and all enabled peripheral
clocks begin running after the oscillator stabilization delay.
The WAIT instruction disables the CPU clock.
After exiting wait mode, the CPU clock and all enabled peripheral
clocks immediately begin running.
Freescale Semiconductor, Inc.
For More Information On This Product,
COP watchdog reset — A timeout of the COP watchdog resets the
MCU, starts the CPU clock, and loads the program counter with
the contents of locations $07FE and $07FF. Software can enable
timer interrupts so that the MCU periodically can exit wait mode to
reset the COP watchdog.
Timer interrupt — Real-time interrupt requests and timer overflow
interrupt requests start the MCU clock and load the program
counter with the contents of locations $07F8 and $07F9.
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Effects of Stop and Wait Modes