MC68HC908SR12CFA Freescale Semiconductor, MC68HC908SR12CFA Datasheet - Page 124
MC68HC908SR12CFA
Manufacturer Part Number
MC68HC908SR12CFA
Description
MICROCONTROLLER 48 PIN
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908SR12MFAE.pdf
(404 pages)
Specifications of MC68HC908SR12CFA
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI
Peripherals
LVD, POR, PWM, Temp Sensor
Number Of I /o
31
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
Q1145673
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC908SR12CFA
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
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Clock Generator Module (CGM)
8.4.7 Special Programming Exceptions
8.4.8 Base Clock Selector Circuit
Data Sheet
124
The programming method described in
does not account for three possible exceptions. A value of 0 for R, N, or
L is meaningless when used in the equations given. To account for these
exceptions:
(See
This circuit is used to select either the oscillator clock, CGMXCLK, or the
divided VCO clock, CGMPCLK, as the source of the base clock,
CGMOUT. The two input clocks go through a transition control circuit
that waits up to three CGMXCLK cycles and three CGMPCLK cycles to
change from one clock source to the other. During this time, CGMOUT
is held in stasis. The output of the transition control circuit is then divided
by two to correct the duty cycle. Therefore, the bus clock frequency,
which is one-half of the base clock frequency, is one-fourth the
frequency of the selected clock (CGMXCLK or CGMPCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives
CGMOUT. The divided VCO clock cannot be selected as the base clock
source if the PLL is not turned on. The PLL cannot be turned off if the
divided VCO clock is selected. The PLL cannot be turned on or off
simultaneously with the selection or deselection of the divided VCO
clock. The divided VCO clock also cannot be selected as the base clock
source if the factor L is programmed to a 0. This value would set up a
condition inconsistent with the operation of the PLL, so that the PLL
would be disabled and the oscillator clock would be forced as the source
of the base clock.
•
•
8.4.8 Base Clock Selector
A 0 value for R or N is interpreted exactly the same as a value of 1.
A 0 value for L disables the PLL and prevents its selection as the
source for the base clock.
Clock Generator Module (CGM)
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
Circuit.)
8.4.6 Programming the PLL
Freescale Semiconductor
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