MC68HC908SR12CFA Freescale Semiconductor, MC68HC908SR12CFA Datasheet - Page 359

• Manufacturer Part Number: MC68HC908SR12CFA
• Description: MICROCONTROLLER 48 PIN
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908SR12CFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, Temp Sensor
• Number Of I /o: 31
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: Q1145673

22.4.1 Polled LVI Operation
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
Freescale Semiconductor
NOTE:
NOTE:
After a power-on reset (POR) the LVI’s default mode of operation is 3V.
If a 5V system is used, the user must set the LVI5OR3 bit to raise the
trip point to 5V operation. Note that this must be done after every power-
on reset since the default will revert back to 3V mode after each power-
on reset. If the V
the 3V mode trip voltage when POR is released, the MCU will operate
because V
care must be taken to ensure that V
after POR is released.
If the user requires 5V mode and sets the LVI5OR3 bit after a power-on
reset while the V
MCU will immediately go into reset. The LVI in this case will hold the
MCU in reset until either V
which will release reset or V
re-trigger the power-on reset and reset the trip point to 3V operation.
LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the configuration
register 1 (CONFIG1). See
Registers (CONFIG & MOR)
Once an LVI reset occurs, the MCU remains in reset until V
above a voltage, V
9.4.2.5 Low-Voltage Inhibit (LVI) Reset
between the SIM and the LVI. The output of the comparator controls the
state of the LVIOUT flag in the LVI status register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
In applications that can operate at V
software can monitor V
register 1 (CONFIG1), the LVIPWRD bit must be at logic 0 to enable the
LVI module, and the LVIRSTD bit must be at logic 1 to disable LVI
resets.
TRIPF
Low-Voltage Inhibit (LVI)
DD
defaults to 3V mode after a POR. So, in a 5V system
DD
TRIPR
supply is below the 5V mode trip voltage but above
supply is not above the V
DD
, which causes the MCU to exit reset. See
DD
by polling the LVIOUT bit. In the configuration
Section 5. Configuration and Mask Option
DD
goes above the rising 5V trip point, V
for details of the LVI’s configuration bits.
decreases to approximately 0V which will
DD
DD
is above the 5V mode trip voltage
levels below the V
for details of the interaction
TRIPF
Low-Voltage Inhibit (LVI)
for 5V mode, the
Functional Description
TRIPF
DD
Data Sheet
rises
level,
TRIPR
359
,