XC68HC705B32CB Freescale Semiconductor, XC68HC705B32CB Datasheet - Page 68

• Manufacturer Part Number: XC68HC705B32CB
• Description: IC MCU 2.1MHZ 32K OTP 56-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of XC68HC705B32CB

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 256 x 8
• Ram Size: 528 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-SDIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

5
The purpose of this procedure is to prevent the OCF1 bit from being set between the time it is read
and the write to the corresponding output compare register.
All bits of the output compare register are readable and writable and are not altered by the timer
hardware or reset. If the compare function is not needed, the two bytes of the output compare
register can be used as storage locations.
5.4.2
The 16-bit output compare register 2 is made up of two 8-bit registers at locations $1E (MSB) and
$1F (LSB). The contents of the output compare register 2 are compared with the contents of the
free-running counter continually and, if a match is found, the corresponding output compare flag
(OCF2) in the timer status register is set and the output level (OLVL2) is transferred to pin TCMP2.
The output compare register 2 values and the output level bit should be changed after each
successful comparison to establish a new elapsed timeout. An interrupt can also accompany a
successful output compare provided the corresponding interrupt enable bit (OCIE) is set. (The
free-running counter is updated every four internal bus clock cycles.)
After a processor write cycle to the output compare register 2 containing the MSB ($1E), the
output compare function is inhibited until the LSB ($1F) is also written. The user must write both
bytes (locations) if the MSB is written first. A write made only to the LSB ($1F) will not inhibit the
compare 2 function. The processor can write to either byte of the output compare register 2 without
affecting the other byte. The output level (OLVL2) bit is clocked to the output level register and
hence to the TCMP2 pin whether the output compare flag 2 (OCF2) is set or clear. The minimum
time required to update the output compare register 2 is a function of the program rather than the
internal hardware. Because the output compare flag 2 and the output compare register 2 are not
defined at power on, and not affected by reset, care must be taken when initializing output
compare functions with software. The following procedure is recommended:
Freescale
5-10
Output compare high 2
Output compare low 2
– Write to output compare high 2 to inhibit further compares;
– Read the timer status register to clear OCF2 (if set);
– Write to output compare low 2 to enable the output compare 2 function.
Output compare register 2 (OCR2)
Address
$001E
$001F
PROGRAMMABLE TIMER
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
MC68HC05B6
bit 0
Undefined
Undefined
Rev. 4.1
on reset
State