XC68HC705B32CB Freescale Semiconductor, XC68HC705B32CB Datasheet - Page 79

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XC68HC705B32CB

Manufacturer Part Number
XC68HC705B32CB
Description
IC MCU 2.1MHZ 32K OTP 56-DIP
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of XC68HC705B32CB

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Eeprom Size
256 x 8
Ram Size
528 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
56-SDIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
If there has been a framing error without detection of a break (10 zeros for 8 bit format or 11 zeros
for 9 bit format), the circuit continues to operate as if there actually was a stop bit, and the start
edge will be placed artificially. The last bit received in the data shift register is inverted to a logic
one, and the three logic one start qualifiers (shown in
register during the interval when detection of a start bit is anticipated (see
the start bit will be accepted no sooner than it is anticipated.
MC68HC05B6
Rev. 4.1
RDI
RDI
RDI
16X internal sampling clock
RT clock edges for all three examples
Idle
1
1
1
Previous bit
RDI
1
1
1
Figure 6-4 SCI examples of start bit sampling technique
1
1
1
Figure 6-5 SCI sampling technique used on all bits
16RT 1RT
1
1
1
SERIAL COMMUNICATIONS INTERFACE
1
1
1
Noise
Present bit
1
1
0
1
1
1
1
1
1
1
1
1
qualifiers
8RT 9RT 10RT
Start
1
1
1
Samples
1
1
1
Start
Start
Start
1RT 2RT 3RT
0
0
0
Figure
0
0
0
verification samples
6-4) are forced into the sample shift
4RT
Start edge
Noise
5RT
16RT 1RT
0
1
0
6RT
Next bit
7RT
0
0
0
Figure
8RT
6-6); therefore,
Freescale
6-7
6

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