HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet

IC H8S MCU FLASH 256K 144-QFP

HD64F2676VFC33

Manufacturer Part Number
HD64F2676VFC33
Description
IC H8S MCU FLASH 256K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2676VFC33

Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
To our customers,
Old Company Name in Catalogs and Other Documents
st
On April 1
, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website:
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
http://www.renesas.com
st
April 1
, 2010
Renesas Electronics Corporation

Related parts for HD64F2676VFC33

HD64F2676VFC33 Summary of contents

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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...

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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...

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H8S/2600 Series, 16 H8S/2000 Series Software Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked ...

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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...

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The H8S/2600 Series and the H8S/2000 Series are built around an H8S/2000 CPU core. The H8S/2600 and H8S/2000 CPUs have the same internal 32-bit architecture. Both CPUs execute basic instructions in one state, have sixteen 16-bit registers, and have a ...

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Rev. 4.00 Feb 24, 2006 page iv of xiv ...

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Main Revisions for This Edition Item Page 1.1.1 Features 2 2.2.22 CLRMAC 90 Operand Format and Number of States Required for Execution 2.2.24 DAA 94 Description 2.2.37 LDMAC 130 Operand Format and Number of States Required for Execution 2.2.42 (1) ...

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Item Page 2.2.64 STMAC 232 Operand Format and Number of States Required for Execution 2.3 Instruction Set 250, 251, Table 2.1 Instruction 260, Set 262 Rev. 4.00 Feb 24, 2006 page vi of xiv Revisions (See Manual for Details) Table ...

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Item Page 2.6 Number of States 283, Required for Instruction 285, Execution 286, 288 Table 2.5 Number of Cycles in Instruction Execution 2.7 Bus States During 290 Instruction Execution Table 2.6 Instruction 293 to Execution Cycles 302 3.3.5 Usage Notes ...

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Rev. 4.00 Feb 24, 2006 page viii of xiv ...

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Section 1 CPU ...................................................................................................................... 1.1 Overview........................................................................................................................... 1.1.1 Features................................................................................................................ 1.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU .................................. 1.1.3 Differences from H8/300 CPU ............................................................................ 1.1.4 Differences from H8/300H CPU.......................................................................... 1.2 CPU Operating Modes ...................................................................................................... 1.3 Address Space................................................................................................................... 10 1.4 Register Configuration...................................................................................................... ...

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AND (W)......................................................................................................... 54 2.2.4 (3) AND (L).......................................................................................................... 55 2.2.5 (1) ANDC ............................................................................................................. 56 2.2.5 (2) ANDC ............................................................................................................. 57 2.2.6 BAND ............................................................................................................. 58 2.2.7 Bcc .................................................................................................................. 60 2.2.8 BCLR .............................................................................................................. 62 2.2.9 BIAND ............................................................................................................ 64 2.2.10 BILD ............................................................................................................... 66 ...

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INC (L)............................................................................................................ 118 2.2.33 JMP ................................................................................................................. 119 2.2.34 JSR .................................................................................................................. 120 2.2.35 (1) LDC (B) .......................................................................................................... 122 2.2.35 (2) LDC (B) .......................................................................................................... 123 2.2.35 (3) LDC (W) ......................................................................................................... 124 2.2.35 (4) LDC (W) ......................................................................................................... 126 2.2.36 LDM................................................................................................................ 128 ...

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ROTL (B) ........................................................................................................ 171 2.2.51 (2) ROTL (B) ........................................................................................................ 172 2.2.51 (3) ROTL (W)....................................................................................................... 173 2.2.51 (4) ROTL (W)....................................................................................................... 174 2.2.51 (5) ROTL (L) ........................................................................................................ 175 2.2.51 (6) ROTL (L) ........................................................................................................ 176 2.2.52 (1) ROTR (B)........................................................................................................ 177 2.2.52 ...

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SHLL (W) ....................................................................................................... 213 2.2.59 (5) SHLL (L)......................................................................................................... 214 2.2.59 (6) SHLL (L)......................................................................................................... 215 2.2.60 (1) SHLR (B) ........................................................................................................ 216 2.2.60 (2) SHLR (B) ........................................................................................................ 217 2.2.60 (3) SHLR (W) ....................................................................................................... 218 2.2.60 (4) SHLR (W) ....................................................................................................... 219 ...

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Trace .................................................................................................................... 312 3.3.4 Interrupt Exception Handling and Trap Instruction Exception Handling ............ 312 3.3.5 Usage Notes ......................................................................................................... 312 3.4 Program Execution State................................................................................................... 314 3.5 Bus-Released State............................................................................................................ 315 3.6 Power-Down State ............................................................................................................ 315 3.6.1 Sleep Mode .......................................................................................................... 315 3.6.2 ...

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Overview The H8S/2600 CPU and the H8S/2000 CPU are high-speed central processing units with a common an internal 32-bit architecture. Each CPU is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU and H8S/2000 CPU have sixteen 16-bit ...

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Section 1 CPU High-speed operation All frequently-used instructions execute in one or two states Maximum clock frequency: 8/16/32-bit register-register add/subtract 8-bit register-register multiply: 16 8-bit register-register divide: 16 16-bit register-register multiply: 32 16-bit register-register divide: Two CPU ...

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Differences from H8/300 CPU In comparison with the H8/300 CPU, the H8S/2600 CPU and H8S/2000 CPU have the following enhancements. More general registers and control registers Eight 16-bit registers, one 8-bit and two 32-bit control registers have been added. ...

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Section 1 CPU 1.1.4 Differences from H8/300H CPU In comparison with the H8/300H CPU, the H8S/2600 CPU and H8S/2000 CPU have the following enhancements. Additional control register One 8-bit and two 32-bit control registers have been added. Expanded address space ...

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CPU Operating Modes Like the H8/300H CPU, the H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 4-Gbyte total address space, of which ...

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Section 1 CPU Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits (figure 1.2). The exception vector ...

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Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown ...

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Section 1 CPU Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits ...

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Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are ...

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Section 1 CPU 1.3 Address Space Figure 1.6 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 4-Gbyte address space in advanced mode. ...

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Register Configuration 1.4.1 Overview The CPUs have the internal registers shown in figure 1.7. There are two types of registers: general registers and control registers. The H8S/2000 CPU does not support the MAC register. General Registers (Rn) and Extended ...

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Section 1 CPU 1.4.2 General Registers The CPUs have eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data ...

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SP (ER7) 1.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), 8-bit condition-code register (CCR), and 64-bit multiply-accumulate register (MAC: H8S/2600 CPU only). (1) Program Counter (PC) This 24-bit counter indicates the ...

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Section 1 CPU Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions. All interrupts, including NMI, are disabled for three states after one of these instructions is executed, except for STC. (3) ...

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Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to the detailed descriptions of the instructions starting in section 2.2.1. Operations can be performed on the CCR ...

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Section 1 CPU 1.5 Data Formats The CPUs can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte ...

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Word data Rn Word data En 15 MSB Longword data ERn 31 MSB En Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: ...

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Section 1 CPU 1.5.2 Memory Data Formats Figure 1.11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address attempt ...

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Instruction Set 1.6.1 Overview The H8S/2600 CPU has 69types of instructions, while the H8S/2000 CPU has 65 types. The instructions are classified by function as shown in table 1.1. For a detailed description of each instruction, see section 2.2, ...

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Section 1 CPU 1.6.2 Instructions and Addressing Modes Table 1.2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU and H8S/2000 CPU can use. Table 1.2 Combinations of Instructions and Addressing Modes — @@aa:8 @(d:16,PC) @(d:8,PC) @aa:32 ...

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Rn #xx Section 1 CPU Rev. 4.00 Feb 24, 2006 page 21 of 322 REJ09B0139-0400 ...

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Section 1 CPU 1.6.3 Table of Instructions Classified by Function Table 1.3 summarizes the instructions in each functional category. The notation used in table 1.3 is defined next. Operation Notation Rd General register (destination)* Rs General register (source)* Rn General ...

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Table 1.3 Instructions Classified by Function Type Instruction Data transfer MOV MOVFPE MOVTPE POP PUSH LDM STM Size * 1 Function B/W/L (EAs) Rd, Rs Moves data between two general registers or between a general register and memory, or moves ...

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Section 1 CPU Type Instruction Arithmetic ADD operations SUB ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU MULXS DIVXU DIVXS Rev. 4.00 Feb 24, 2006 page 24 of 322 REJ09B0139-0400 Size * 1 Function B/W Rd, Rd ...

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Type Instruction Arithmetic CMP operations NEG EXTU EXTS TAS MAC CLRMAC LDMAC STMAC Size * 1 Function B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, ...

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Section 1 CPU Type Instruction Logic operations AND OR XOR NOT Shift operations SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Rev. 4.00 Feb 24, 2006 page 26 of 322 REJ09B0139-0400 Size * 1 Function B/W Rd, Rd ...

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Type Instruction Bit-manipulation BSET instructions BCLR BNOT BTST BAND BIAND BOR BIOR Size * 1 Function B 1 (<bit-No.> of <EAd>) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by ...

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Section 1 CPU Type Instruction Bit-manipulation BXOR instructions BIXOR BLD BILD BST BIST Rev. 4.00 Feb 24, 2006 page 28 of 322 REJ09B0139-0400 Size * 1 Function B C (<bit-No.> of <EAd>) Exclusive-ORs the carry flag with a specified bit ...

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Type Instruction Branch Bcc instructions JMP BSR JSR RTS Size * 1 Function — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description BRA(BT) Always (true) BRN(BF) Never (false) BHI ...

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Section 1 CPU Type Instruction System control TRAPA instructions RTE SLEEP LDC STC ANDC ORC XORC NOP Rev. 4.00 Feb 24, 2006 page 30 of 322 REJ09B0139-0400 Size * 1 Function — Starts trap-instruction exception handling. — Returns from an ...

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Type Instruction Block data EEPMOV.B transfer instruction EEPMOV.W Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Size * ...

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Section 1 CPU 1.6.4 Basic Instruction Formats The H8S/2600 or H8S/2000 instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition ...

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Addressing Modes and Effective Address Calculation (1) Addressing Modes The CPUs support the eight addressing modes listed in table 1.4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and ...

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Section 1 CPU 4. Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn: Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is ...

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Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in ...

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Section 1 CPU If an odd address is specified in word or longword memory access branch address, the least significant bit is regarded as 0, causing data to be accessed or an instruction code to be fetched ...

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Table 1.6 Effective Address Calculation Section 1 CPU Rev. 4.00 Feb 24, 2006 page 37 of 322 REJ09B0139-0400 ...

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Section 1 CPU Rev. 4.00 Feb 24, 2006 page 38 of 322 REJ09B0139-0400 ...

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Section 1 CPU Rev. 4.00 Feb 24, 2006 page 39 of 322 REJ09B0139-0400 ...

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Section 1 CPU Rev. 4.00 Feb 24, 2006 page 40 of 322 REJ09B0139-0400 ...

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Section 2 Instruction Descriptions 2.1 Tables and Symbols This section explains how to read the tables in section 2.2, describing each instruction. Note that the descriptions of some instructions extend over more than one page. [1] Mnemonic (Full Name) [3] ...

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Section 2 Instruction Descriptions 2.1.1 Assembly-Language Format Example: ADD. B <EAs>, Rd Size Mnemonic The operand size is byte (B), word (W), or longword (L). Some instructions are restricted to a limited set of operand sizes. The symbol <EA> indicates ...

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Operation The symbols used in the operation descriptions are defined as follows. Rd General register (destination)* Rs General register (source)* Rn General register* ERn General register (32-bit register) MAC Multiply-accumulate register (32-bit register) (EAd) Destination operand (EAs) Source operand ...

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Section 2 Instruction Descriptions 2.1.3 Condition Code The symbols used in the condition-code description are defined as follows. Symbol Meaning Changes according to the result of instruction execution Undetermined (no guaranteed value Always cleared Always ...

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Register Specification Address Register Specification: When a general register is used as an address register [@ERn, @(d:16, ERn), @(d:32, ERn), @ERn+, or @–ERn], the register is specified by a 3-bit register field (ers or erd). Data Register Specification: A ...

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Section 2 Instruction Descriptions 2.1.6 Bit Data Access in Bit Manipulation Instructions Bit data is accessed as the n-th bit ( … byte operand in a general register or memory. The bit ...

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Instruction Descriptions The instructions are described starting in section 2.2.1. Section 2 Instruction Descriptions Rev. 4.00 Feb 24, 2006 page 47 of 322 REJ09B0139-0400 ...

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Section 2 Instruction Descriptions 2.2.1 (1) ADD (B) ADD (ADD Binary) Operation Rd + (EAs) Rd Assembly-Language Format ADD.B <EAs>, Rd Operand Size Byte Description This instruction adds the source operand to the contents of an 8-bit register Rd (destination ...

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ADD (W) ADD (ADD Binary) Operation Rd + (EAs) Rd Assembly-Language Format ADD.W <EAs>, Rd Operand Size Word Description This instruction adds the source operand to the contents of a 16-bit register Rd (destination operand) and stores the ...

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Section 2 Instruction Descriptions 2.2.1 (3) ADD (L) ADD (ADD Binary) Operation ERd + (EAs) ERd Assembly-Language Format ADD.L <EAs>, ERd Operand Size Longword Description This instruction adds the source operand to the contents of a 32-bit register ERd (destination ...

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ADDS ADDS (ADD with Sign extension) Operation ERd ERd ERd Assembly-Language Format ADDS #1, ERd ADDS #2, ERd ADDS #4, ERd Operand Size Longword Description This instruction adds the immediate ...

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Section 2 Instruction Descriptions 2.2.3 ADDX ADDX (ADD with eXtend carry) Operation Rd + (EAs Assembly-Language Format ADDX <EAs>, Rd Operand Size Byte Description This instruction adds the source operand and carry flag to the contents of ...

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AND (B) AND (AND logical) Operation Rd (EAs) Rd Assembly-Language Format AND.B <EAs>, Rd Operand Size Byte Description This instruction ANDs the source operand with the contents of an 8-bit register Rd (destination operand) and stores the result ...

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Section 2 Instruction Descriptions 2.2.4 (2) AND (W) AND (AND logical) Operation Rd (EAs) Rd Assembly-Language Format AND.W <EAs>, Rd Operand Size Word Description This instruction ANDs the source operand with the contents of a 16-bit register Rd (destination operand) ...

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AND (L) AND (AND logical) Operation ERd (EAs) ERd Assembly-Language Format AND.L <EAs>, ERd Operand Size Longword Description This instruction ANDs the source operand with the contents of a 32-bit register ERd (destination operand) and stores the result ...

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Section 2 Instruction Descriptions 2.2.5 (1) ANDC ANDC (AND Control register) Operation CCR #IMM CCR Assembly-Language Format ANDC #xx:8, CCR Operand Size Byte Description This instruction ANDs the contents of the condition-code register (CCR) with immediate data and stores the ...

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ANDC ANDC (AND Control register) Operation EXR #IMM EXR Assembly-Language Format ANDC #xx:8, EXR Operand Size Byte Description This instruction ANDs the contents of the extended control register (EXR) with immediate data and stores the result in the ...

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Section 2 Instruction Descriptions 2.2.6 BAND BAND (Bit AND) Operation C (<bit No.> of <EAd>) Assembly-Language Format BAND #xx:3, <EAd> Operand Size Byte Description This instruction ANDs a specified bit in the destination operand with the carry flag and stores ...

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BAND (Bit AND) Section 2 Instruction Descriptions Bit Logical AND Rev. 4.00 Feb 24, 2006 page 59 of 322 REJ09B0139-0400 ...

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Section 2 Instruction Descriptions 2.2.7 Bcc Bcc (Branch conditionally) Operation If condition is true, then PC + disp PC else next; Assembly-Language Format Bcc disp Condition field Operand Size — Description If the condition specified in the condition field (cc) ...

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Bcc (Branch conditionally) Operand Format and Number of States Required for Execution Addressing Mnemonic Mode Program-counter BRA (BT) relative Program-counter BRN (BF) relative Program-counter BHI relative Program-counter BLS relative Program-counter Bcc (BHS) relative Program-counter BCS (BLO) relative Program-counter BNE relative ...

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Section 2 Instruction Descriptions 2.2.8 BCLR BCLR (Bit CLeaR) Operation 0 (<bit No.> of <EAd>) Assembly-Language Format BCLR #xx:3, <EAd> BCLR Rn, <EAd> Operand Size Byte Description This instruction clears a specified bit in the destination operand to 0. The ...

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BCLR (Bit CLeaR) Section 2 Instruction Descriptions Rev. 4.00 Feb 24, 2006 page 63 of 322 REJ09B0139-0400 Bit Clear ...

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Section 2 Instruction Descriptions 2.2.9 BIAND BIAND (Bit Invert AND) Operation C [ (<bit No.> of <EAd>)] Assembly-Language Format BIAND #xx:3, <EAd> Operand Size Byte Description This instruction ANDs the inverse of a specified bit in the destination operand with ...

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BIAND (Bit Invert AND) Section 2 Instruction Descriptions Bit Logical AND Rev. 4.00 Feb 24, 2006 page 65 of 322 REJ09B0139-0400 ...

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Section 2 Instruction Descriptions 2.2.10 BILD BILD (Bit Invert LoaD) Operation (<bit No.> of <EAd>) C Assembly-Language Format BILD #xx:3, <EAd> Operand Size Byte Description This instruction loads the inverse of a specified bit from the destination operand into the ...

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BILD (Bit Invert LoaD) Section 2 Instruction Descriptions Rev. 4.00 Feb 24, 2006 page 67 of 322 REJ09B0139-0400 Bit Load ...

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Section 2 Instruction Descriptions 2.2.11 BIOR BIOR (Bit Invert inclusive OR) Operation C [ (<bit No.> of <EAd>)] Assembly-Language Format BIOR #xx:3, <EAd> Operand Size Byte Description This instruction ORs the inverse of a specified bit in the destination operand ...

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BIOR (Bit Invert inclusive OR) Section 2 Instruction Descriptions Bit Logical OR Rev. 4.00 Feb 24, 2006 page 69 of 322 REJ09B0139-0400 ...

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Section 2 Instruction Descriptions 2.2.12 BIST BIST (Bit Invert STore) Operation C (<bit No.> of <EAd>) Assembly-Language Format BIST #xx:3, <EAd> Operand Size Byte Description This instruction stores the inverse of the carry flag in a specified bit location in ...

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BIST (Bit Invert STore) Section 2 Instruction Descriptions Rev. 4.00 Feb 24, 2006 page 71 of 322 REJ09B0139-0400 Bit Store ...

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Section 2 Instruction Descriptions 2.2.13 BIXOR BIXOR (Bit Invert eXclusive OR) Operation C [ (<bit No.> of <EAd>)] Assembly-Language Format BIXOR #xx:3, <EAd> Operand Size Byte Description This instruction exclusively ORs the inverse of a specified bit in the destination ...

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BIXOR (Bit Invert eXclusive OR) Section 2 Instruction Descriptions Bit Exclusive Logical OR Rev. 4.00 Feb 24, 2006 page 73 of 322 REJ09B0139-0400 ...

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Section 2 Instruction Descriptions 2.2.14 BLD BLD (Bit LoaD) Operation (<Bit No.> of <EAd>) C Assembly-Language Format BLD #xx:3, <EAd> Operand Size Byte Description This instruction loads a specified bit from the destination operand into the carry flag. The bit ...

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BLD (Bit LoaD) Section 2 Instruction Descriptions Rev. 4.00 Feb 24, 2006 page 75 of 322 REJ09B0139-0400 Bit Load ...

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Section 2 Instruction Descriptions 2.2.15 BNOT BNOT (Bit NOT) Operation (<bit No.> of <EAd>) (bit No. of <EAd>) Assembly-Language Format BNOT #xx:3, <EAd> BNOT Rn, <EAd> Operand Size Byte Description This instruction inverts a specified bit in the destination operand. ...

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BNOT (Bit NOT) Section 2 Instruction Descriptions Rev. 4.00 Feb 24, 2006 page 77 of 322 REJ09B0139-0400 Bit NOT ...

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Section 2 Instruction Descriptions 2.2.16 BOR BOR (Bit inclusive OR) Operation C (<bit No.> of <EAd>) Assembly-Language Format BOR #xx:3, <EAd> Operand Size Byte Description This instruction ORs a specified bit in the destination operand with the carry flag and ...

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BOR (Bit inclusive OR) Section 2 Instruction Descriptions Bit Logical OR Rev. 4.00 Feb 24, 2006 page 79 of 322 REJ09B0139-0400 ...

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Section 2 Instruction Descriptions 2.2.17 BSET BSET (Bit SET) Operation 1 (<bit No.> of <EAd>) Assembly-Language Format BSET #xx:3, <EAd> BSET Rn, <EAd> Operand Size Byte Description This instruction sets a specified bit in the destination operand to 1. The ...

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BSET (Bit SET) Section 2 Instruction Descriptions Rev. 4.00 Feb 24, 2006 page 81 of 322 REJ09B0139-0400 Bit Set ...

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Section 2 Instruction Descriptions 2.2.18 BSR BSR (Branch to SubRoutine) Operation PC @– disp PC Assembly-Language Format BSR disp Operand Size — Description This instruction branches to a subroutine at a specified address. It pushes the program counter ...

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BSR (Branch to SubRoutine) Notes The stack structure differs between normal mode and advanced mode. In normal mode only the lower 16 bits of the program counter are pushed onto the stack. Ensure that the branch destination address is even. ...

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Section 2 Instruction Descriptions 2.2.19 BST BST (Bit STore) Operation C (<bit No.> of <EAd>) Assembly-Language Format BST #xx:3, <EAd> Operand Size Byte Description This instruction stores the carry flag in a specified bit location in the destination operand. The ...

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BST (Bit STore) Section 2 Instruction Descriptions Rev. 4.00 Feb 24, 2006 page 85 of 322 REJ09B0139-0400 Bit Store ...

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Section 2 Instruction Descriptions 2.2.20 BTST BTST (Bit TeST) Operation (<Bit No.> of <EAd>) Z Assembly-Language Format BTST #xx:3, <EAd> BTST Rn, <EAd> Operand Size Byte Description This instruction tests a specified bit in the destination operand and sets or ...

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BTST (Bit TeST) Section 2 Instruction Descriptions Rev. 4.00 Feb 24, 2006 page 87 of 322 REJ09B0139-0400 Bit Test ...

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Section 2 Instruction Descriptions 2.2.21 BXOR BXOR (Bit eXclusive OR) Operation C (<bit No.> of <EAd>) Assembly-Language Format BXOR #xx:3, <EAd> Operand Size Byte Description This instruction exclusively ORs a specified bit in the destination operand with the carry flag ...

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BXOR (Bit eXclusive OR) Section 2 Instruction Descriptions Bit Exclusive Logical OR Rev. 4.00 Feb 24, 2006 page 89 of 322 REJ09B0139-0400 ...

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Section 2 Instruction Descriptions 2.2.22 CLRMAC CLRMAC (CLeaR MAC register) Operation 0 MACH, MACL Assembly-Language Format CLRMAC Operand Size — Description This instruction simultaneously clears registers MACH and MACL supported only by the H8S/2600 CPU. Operand Format and ...

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CMP (B) CMP (CoMPare) Operation Rd – (EAs), set/clear CCR Assembly-Language Format CMP.B <EAs>, Rd Operand Size Byte Description This instruction subtracts the source operand from the contents of an 8-bit register Rd (destination operand) and sets or ...

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Section 2 Instruction Descriptions 2.2.23 (2) CMP (W) CMP (CoMPare) Operation Rd – (EAs), set/clear CCR Assembly-Language Format CMP.W <EAs>, Rd Operand Size Word Description This instruction subtracts the source operand from the contents of a 16-bit register Rd (destination ...

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CMP (L) CMP (CoMPare) Operation ERd – (EAs), set/clear CCR Assembly-Language Format CMP.L <EAs>, ERd Operand Size Longword Description This instruction subtracts the source operand from the contents of a 32-bit register ERd (destination operand) and sets or ...

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Section 2 Instruction Descriptions 2.2.24 DAA DAA (Decimal Adjust Add) Operation Rd (decimal adjust) Rd Assembly-Language Format DAA Rd Operand Size Byte Description Given that the result of an addition operation performed by an ADD.B or ADDX instruction on 4-bit ...

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DAA (Decimal Adjust Add) Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mnemonic Mode Register direct DAA Notes Valid results (8-bit register Rd contents and ...

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Section 2 Instruction Descriptions 2.2.25 DAS DAS (Decimal Adjust Subtract) Operation Rd (decimal adjust) Rd Assembly-Language Format DAS Rd Operand Size Byte Description Given that the result of a subtraction operation performed by a SUB.B, SUBX.B, or NEG.B instruction on ...

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DAS (Decimal Adjust Subtract) Operand Format and Number of States Required for Execution Addressing Mnemonic Mode Register direct DAS Notes Valid results (8-bit register Rd contents and and H flags) are not assured if this instruction ...

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Section 2 Instruction Descriptions 2.2.26 (1) DEC (B) DEC (DECrement) Operation Rd – Assembly-Language Format DEC.B Rd Operand Size Byte Description This instruction decrements an 8-bit register Rd (destination operand) and stores the result in the 8-bit register ...

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DEC (W) DEC (DECrement) Operation Rd – – Assembly-Language Format DEC.W #1, Rd DEC.W #2, Rd Operand Size Word Description This instruction subtracts the immediate value from the contents of ...

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Section 2 Instruction Descriptions 2.2.26 (3) DEC (L) DEC (DECrement) Operation ERd – 1 ERd ERd – 2 ERd Assembly-Language Format DEC.L #1, ERd DEC.L #2, ERd Operand Size Longword Description This instruction subtracts the immediate value ...

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DIVXS (B) DIVXS (DIVide eXtend as Signed) Operation Assembly-Language Format DIVXS.B Rs, Rd Operand Size Byte Description This instruction divides the contents of a 16-bit register Rd (destination operand) by the contents of an 8-bit ...

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Section 2 Instruction Descriptions DIVXS (DIVide eXtend as Signed) Operand Format and Number of States Required for Execution Addressing Mnemonic Mode Register direct DIVXS.B Notes The N flag is set the dividend and divisor have different signs, ...

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DIVXS (W) DIVXS (DIVide eXtend as Signed) Operation ERd Rs ERd Assembly-Language Format DIVXS.W Rs, ERd Operand Size Word Description This instruction divides the contents of a 32-bit register ERd (destination operand) by the contents of a 16-bit ...

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Section 2 Instruction Descriptions DIVXS (DIVide eXtend as Signed) Operand Format and Number of States Required for Execution Addressing Mnemonic Mode Register direct DIVXS.W Notes The N flag is set the dividend and divisor have different signs, ...

Page 121

DIVXU (B) DIVXU (DIVide eXtend as Unsigned) Operation Assembly-Language Format DIVXU.B Rs, Rd Operand Size Byte Description This instruction divides the contents of a 16-bit register Rd (destination operand) by the contents of an 8-bit ...

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Section 2 Instruction Descriptions DIVXU (DIVide eXtend as Unsigned) Operand Format and Number of States Required for Execution Addressing Mnemonic Mode Register direct DIVXU.B Notes Rev. 4.00 Feb 24, 2006 page 106 of 322 REJ09B0139-0400 Instruction Format Operands 1st byte ...

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DIVXU (W) DIVXU (DIVide eXtend as Unsigned) Operation ERd Rs ERd Assembly-Language Format DIVXU.W Rs, ERd Operand Size Word Description This instruction divides the contents of a 32-bit register ERd (destination operand) by the contents of a 16-bit ...

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Section 2 Instruction Descriptions DIVXU (DIVide eXtend as Unsigned) Operand Format and Number of States Required for Execution Addressing Mnemonic Mode Register direct DIVXU.W Notes Rev. 4.00 Feb 24, 2006 page 108 of 322 REJ09B0139-0400 Instruction Format Operands 1st byte ...

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EEPMOV (B) EEPMOV (MOVe data to EEPROM) Operation if R4L 0 then repeat @ER5+ @ER6+ R4L – 1 R4L until R4L = 0 else next; Assembly-Language Format EEPMOV.B Operand Size — Description This instruction performs a block data ...

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Section 2 Instruction Descriptions 2.2.29 (2) EEPMOV (W) EEPMOV (MOVe data to EEPROM) Operation then repeat @ER5+ @ER6+ R4 – until else next; Assembly-Language Format EEPMOV.W Operand Size — Description This instruction ...

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EEPMOV (MOVe data to EEPROM) Operand Format and Number of States Required for Execution Addressing Mnemonic Mode — EEPMOV.W Note the initial value of R4. Although n bytes of data are transferred, 2 data accesses ...

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Section 2 Instruction Descriptions 2.2.30 (1) EXTS (W) EXTS (EXTend as Signed) Operation (<Bit 7> of Rd) (<bits 15 to 8> of Rd) Assembly-Language Format EXTS.W Rd Operand Size Word Description This instruction copies the sign of the lower 8 ...

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EXTS (L) EXTS (EXTend as Signed) Operation (<Bit 15> of ERd) (<bits 31 to 16> of ERd) Assembly-Language Format EXTS.L ERd Operand Size Longword Description This instruction copies the sign of the lower 16 bits in a 32-bit ...

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Section 2 Instruction Descriptions 2.2.31 (1) EXTU (W) EXTU (EXTend as Unsigned) Operation 0 (<bits 15 to 8> of Rd) Assembly-Language Format EXTU.W Rd Operand Size Word Description This instruction extends the lower 8 bits in a 16-bit register Rd ...

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EXTU (L) EXTU (EXTend as Unsigned) Operation 0 (<bits 31 to 16> of ERd) Assembly-Language Format EXTU.L ERd Operand Size Longword Description This instruction extends the lower 16 bits (general register Rd 32-bit register ERd to ...

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Section 2 Instruction Descriptions 2.2.32 (1) INC (B) INC (INCrement) Operation Assembly-Language Format INC.B Rd Operand Size Byte Description This instruction increments an 8-bit register Rd (destination operand) and stores the result in the 8-bit register ...

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INC (W) INC (INCrement) Operation Assembly-Language Format INC.W #1, Rd INC.W #2, Rd Operand Size Word Description This instruction adds the immediate value the contents of ...

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Section 2 Instruction Descriptions 2.2.32 (3) INC (L) INC (INCrement) Operation ERd + 1 ERd ERd + 2 ERd Assembly-Language Format INC.L #1, ERd INC.L #2, ERd Operand Size Longword Description This instruction adds the immediate value ...

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JMP JMP (JuMP) Operation Effective address PC Assembly-Language Format JMP <EA> Operand Size — Description This instruction branches unconditionally to a specified effective address. Available Registers ERn: ER0 to ER7 Operand Format and Number of States Required for Execution ...

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Section 2 Instruction Descriptions 2.2.34 JSR JSR (Jump to SubRoutine) Operation PC @–SP Effective address PC Assembly-Language Format JSR <EA> Operand Size — Description This instruction pushes the program counter onto the stack as a return address, then branches to ...

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JSR (Jump to SubRoutine) Notes The stack structure differs between normal mode and advanced mode. In normal mode only the lower 16 bits of the program counter are pushed onto the stack. Ensure that the branch destination address is even. ...

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Section 2 Instruction Descriptions 2.2.35 (1) LDC (B) LDC (LoaD to Control register) Operation <EAs> CCR Assembly-Language Format LDC.B <EAs>, CCR Operand Size Byte Description This instruction loads the source operand contents into the condition-code register (CCR). No interrupt requests, ...

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LDC (B) LDC (LoaD to Control register) Operation <EAs> EXR Assembly-Language Format LDC.B <EAs>, EXR Operand Size Byte Description This instruction loads the source operand contents into the extended control register (EXR). No interrupt requests, including NMI, are ...

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Section 2 Instruction Descriptions 2.2.35 (3) LDC (W) LDC (LoaD to Control register) Operation (EAs) CCR Assembly-Language Format LDC.W <EAs>, CCR Operand Size Word Description This instruction loads the source operand contents into the condition-code register (CCR). Although CCR is ...

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LDC (LoaD to Control register) Section 2 Instruction Descriptions Rev. 4.00 Feb 24, 2006 page 125 of 322 REJ09B0139-0400 Load CCR ...

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Section 2 Instruction Descriptions 2.2.35 (4) LDC (W) LDC (LoaD to Control register) Operation (EAs) EXR Assembly-Language Format LDC.W <EAs>, EXR Operand Size Word Description This instruction loads the source operand contents into the extended control register (EXR). Although EXR ...

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LDC (LoaD to Control register) Section 2 Instruction Descriptions Rev. 4.00 Feb 24, 2006 page 127 of 322 REJ09B0139-0400 Load EXR ...

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Section 2 Instruction Descriptions 2.2.36 LDM LDM (LoaD to Multiple registers) Operation @SP+ ERn (register list) Assembly-Language Format LDM.L @SP+, <register list> Operand Size Longword Description This instruction restores data saved on the stack to a specified list of registers. ...

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LDM (LoaD to Multiple registers) Operand Format and Number of States Required for Execution Addressing Mnemonic Operands Mode @SP+, — LDM.L (ERn–ERn+1) @SP+, — LDM.L (ERn–ERn+2) @SP+, — LDM.L (ERn–ERn+3) Notes Section 2 Instruction Descriptions Instruction Format 1st byte 2nd ...

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Section 2 Instruction Descriptions 2.2.37 LDMAC LDMAC (LoaD to MAC register) Operation ERs MACH or ERs MACL Assembly-Language Format LDMAC ERs, MAC register Operand Size Longword Description This instruction moves the contents of a general register to a multiply-accumulate register ...

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MAC MAC (Multiply and ACcumulate) Operation (EAn) (EAm) + MAC register MAC register ERn + 2 ERn ERm + 2 ERm Assembly-Language Format MAC @ERn+, @ERm+ Operand Size — Description This instruction performs signed multiplication on two 16-bit operands ...

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Section 2 Instruction Descriptions MAC (Multiply and ACcumulate) Operand Format and Number of States Required for Execution Addressing Mnemonic Operands Mode Register @ERn+, indirect with MAC @ERm+ post-increment Notes 1. Flags ( indicating the result of the MAC ...

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MAC (Multiply and ACcumulate) • Z-MULT (zero flag) Saturating mode Non-saturating mode • V-MULT (overflow flag) Saturating mode Non-saturating mode The N-MULT, Z-MULT, and V-MULT flags are not modified by switching between saturating and non-saturating modes execution of ...

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Section 2 Instruction Descriptions 2.2.39 (1) MOV (B) MOV (MOVe data) Operation Rs Rd Assembly-Language Format MOV.B Rs, Rd Operand Size Byte Description This instruction transfers one byte of data from an 8-bit register 8-bit register Rd, ...

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MOV (W) MOV (MOVe data) Operation Rs Rd Assembly-Language Format MOV.W Rs, Rd Operand Size Word Description This instruction transfers one word of data from a 16-bit register 16-bit register Rd, tests the transferred data, ...

Page 152

Section 2 Instruction Descriptions 2.2.39 (3) MOV (L) MOV (MOVe data) Operation ERs ERd Assembly-Language Format MOV.L ERs, ERd Operand Size Longword Description This instruction transfers one word of data from a 32-bit register ERs to a 32-bit register ERd, ...

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MOV (B) MOV (MOVe data) Operation (EAs) Rd Assembly-Language Format MOV.B <EAs>, Rd Operand Size Byte Description This instruction transfers the source operand contents to an 8-bit register Rd, tests the transferred data, and sets condition-code flags according ...

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Section 2 Instruction Descriptions MOV (MOVe data) Rev. 4.00 Feb 24, 2006 page 138 of 322 REJ09B0139-0400 Move ...

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MOV (W) MOV (MOVe data) Operation (EAs) Rd Assembly-Language Format MOV.W <EAs>, Rd Operand Size Word Description This instruction transfers the source operand contents to a 16-bit register Rd, tests the transferred data, and sets condition-code flags according ...

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Section 2 Instruction Descriptions MOV (MOVe data) Rev. 4.00 Feb 24, 2006 page 140 of 322 REJ09B0139-0400 Move ...

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MOV (L) MOV (MOVe data) Operation (EAs) ERd Assembly-Language Format MOV.L <EAs>, ERd Operand Size Longword Description This instruction transfers the source operand contents to a specified 32-bit register (ERd), tests the transferred data, and sets condition-code flags ...

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Section 2 Instruction Descriptions MOV (MOVe data) Rev. 4.00 Feb 24, 2006 page 142 of 322 REJ09B0139-0400 Move ...

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MOV (B) MOV (MOVe data) Operation Rs (EAd) Assembly-Language Format MOV.B Rs, <EAd> Operand Size Byte Description This instruction transfers the contents of an 8-bit register Rs (source operand destination location, tests the transferred data, and ...

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Section 2 Instruction Descriptions MOV (MOVe data) Rev. 4.00 Feb 24, 2006 page 144 of 322 REJ09B0139-0400 Move ...

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MOV (W) MOV (MOVe data) Operation Rs (EAd) Assembly-Language Format MOV.W Rs, <EAd> Operand Size Word Description This instruction transfers the contents of a 16-bit register Rs (source operand destination location, tests the transferred data, and ...

Page 162

Section 2 Instruction Descriptions MOV (MOVe data) Rev. 4.00 Feb 24, 2006 page 146 of 322 REJ09B0139-0400 Move ...

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MOV (L) MOV (MOVe data) Operation ERs (EAd) Assembly-Language Format MOV.L ERs, <EAd> Operand Size Longword Description This instruction transfers the contents of a 32-bit register ERs (source operand destination location, tests the transferred data, and ...

Page 164

Section 2 Instruction Descriptions MOV (MOVe data) Rev. 4.00 Feb 24, 2006 page 148 of 322 REJ09B0139-0400 Move ...

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MOVFPE MOVFPE (MOVe From Peripheral with E clock) Operation (EAs) Rd Synchronized with E clock Assembly-Language Format MOVFPE @aa:16, Rd Operand Size Byte Description This instruction transfers memory contents specified by a 16-bit absolute address to a general register ...

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Section 2 Instruction Descriptions 2.2.41 MOVTPE MOVTPE (MOVe To Peripheral with E clock) Operation Rs (EAd) Synchronized with E clock Assembly-Language Format MOVTPE Rs, @aa:16 Operand Size Byte Description This instruction transfers the contents of a general register Rs (source ...

Page 167

MULXS (B) MULXS (MULtiply eXtend as Signed) Operation Assembly-Language Format MULXS.B Rs, Rd Operand Size Byte Description This instruction multiplies the lower 8 bits of a 16-bit register Rd (destination operand) by the contents of ...

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Section 2 Instruction Descriptions 2.2.42 (2) MULXS (W) MULXS (MULtiply eXtend as Signed) Operation ERd Rs ERd Assembly-Language Format MULXS.W Rs, ERd Operand Size Word Description This instruction multiplies the lower 16 bits of a 32-bit register ERd (destination operand) ...

Page 169

MULXU (B) MULXU (MULtiply eXtend as Unsigned) Operation Assembly-Language Format MULXU.B Rs, Rd Operand Size Byte Description This instruction multiplies the lower 8 bits of a 16-bit register Rd (destination operand) by the contents of ...

Page 170

Section 2 Instruction Descriptions 2.2.43 (2) MULXU (W) MULXU (MULtiply eXtend as Unsigned) Operation ERd Rs ERd Assembly-Language Format MULXU.W Rs, ERd Operand Size Word Description This instruction multiplies the lower 16 bits of a 32-bit register ERd (destination operand) ...

Page 171

NEG (B) NEG (NEGate) Operation 0 – Assembly-Language Format NEG.B Rd Operand Size Byte Description This instruction takes the two’s complement of the contents of an 8-bit register Rd (destination operand) and stores the result in ...

Page 172

Section 2 Instruction Descriptions 2.2.44 (2) NEG (W) NEG (NEGate) Operation 0 – Assembly-Language Format NEG.W Rd Operand Size Word Description This instruction takes the two’s complement of the contents of a 16-bit register Rd (destination operand) and ...

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NEG (L) NEG (NEGate) Operation 0 – ERd ERd Assembly-Language Format NEG.L ERd Operand Size Longword Description This instruction takes the two’s complement of the contents of a 32-bit register ERd (destination operand) and stores the result in ...

Page 174

Section 2 Instruction Descriptions 2.2.45 NOP NOP (No OPeration) Operation Assembly-Language Format NOP Operand Size — Description This instruction only increments the program counter, causing the next instruction to be executed. The internal state of the ...

Page 175

NOT (B) NOT (NOT = logical complement) Operation Rd Rd Assembly-Language Format NOT.B Rd Operand Size Byte Description This instruction takes the one’s complement of the contents of an 8-bit register Rd (destination operand) and stores the result ...

Page 176

Section 2 Instruction Descriptions 2.2.46 (2) NOT (W) NOT (NOT = logical complement) Operation Rd Rd Assembly-Language Format NOT.W Rd Operand Size Word Description This instruction takes the one’s complement of the contents of a 16-bit register Rd (destination operand) ...

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NOT (L) NOT (NOT = logical complement) Operation ERd ERd Assembly-Language Format NOT.L ERd Operand Size Longword Description This instruction takes the one’s complement of the contents of a 32-bit register ERd (destination operand) and stores the result ...

Page 178

Section 2 Instruction Descriptions 2.2.47 (1) OR (B) OR (inclusive OR logical) Operation Rd (EAs) Rd Assembly-Language Format OR.B <EAs>, Rd Operand Size Byte Description This instruction ORs the source operand with the contents of an 8-bit register Rd (destination ...

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OR (W) OR (inclusive OR logical) Operation Rd (EAs) Rd Assembly-Language Format OR.W <EAs>, Rd Operand Size Word Description This instruction ORs the source operand with the contents of a 16-bit register Rd (destination operand) and stores the ...

Page 180

Section 2 Instruction Descriptions 2.2.47 (3) OR (L) OR (inclusive OR logical) Operation ERd (EAs) ERd Assembly-Language Format OR.L <EAs>, ERd Operand Size Longword Description This instruction ORs the source operand with the contents of a 32-bit register ERd (destination ...

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ORC ORC (inclusive OR Control register) Operation CCR #IMM CCR Assembly-Language Format ORC #xx:8, CCR Operand Size Byte Description This instruction ORs the contents of the condition-code register (CCR) with immediate data and stores the result in the ...

Page 182

Section 2 Instruction Descriptions 2.2.48 (2) ORC ORC (inclusive OR Control register) Operation EXR #IMM EXR Assembly-Language Format ORC #xx:8, EXR Operand Size Byte Description This instruction ORs the contents of the extended control register (EXR) with immediate data and ...

Page 183

POP (W) POP (POP data) Operation @SP+ Rn Assembly-Language Format POP.W Rn Operand Size Word Description This instruction restores data from the stack to a 16-bit general register Rn, tests the restored data, and sets condition-code flags according ...

Page 184

Section 2 Instruction Descriptions 2.2.49 (2) POP (L) POP (POP data) Operation @SP+ ERn Assembly-Language Format POP.L ERn Operand Size Longword Description This instruction restores data from the stack to a 32-bit general register ERn, tests the restored data, and ...

Page 185

PUSH (W) PUSH (PUSH data) Operation Rn @–SP Assembly-Language Format PUSH.W Rn Operand Size Word Description This instruction saves data from a 16-bit register Rn onto the stack, tests the saved data, and sets condition-code flags according to ...

Page 186

Section 2 Instruction Descriptions 2.2.50 (2) PUSH (L) PUSH (PUSH data) Operation ERn @–SP Assembly-Language Format PUSH.L ERn Operand Size Longword Description This instruction pushes data from a 32-bit register ERn onto the stack, tests the saved data, and sets ...

Page 187

ROTL (B) ROTL (ROTate Left) Operation Rd (left rotation) Rd Assembly-Language Format ROTL.B Rd Operand Size Byte Description This instruction rotates the bits in an 8-bit register Rd (destination operand) one bit to the left. The most significant ...

Page 188

Section 2 Instruction Descriptions 2.2.51 (2) ROTL (B) ROTL (ROTate Left) Operation Rd (left rotation) Rd Assembly-Language Format ROTL.B #2, Rd Operand Size Byte Description This instruction rotates the bits in an 8-bit register Rd (destination operand) two bits to ...

Page 189

ROTL (W) ROTL (ROTate Left) Operation Rd (left rotation) Rd Assembly-Language Format ROTL.W Rd Operand Size Word Description This instruction rotates the bits in a 16-bit register Rd (destination operand) one bit to the left. The most significant ...

Page 190

Section 2 Instruction Descriptions 2.2.51 (4) ROTL (W) ROTL (ROTate Left) Operation Rd (left rotation) Rd Assembly-Language Format ROTL.W #2, Rd Operand Size Word Description This instruction rotates the bits in a 16-bit register Rd (destination operand) two bits to ...

Page 191

ROTL (L) ROTL (ROTate Left) Operation ERd (left rotation) ERd Assembly-Language Format ROTL.L ERd Operand Size Longword Description This instruction rotates the bits in a 32-bit register ERd (destination operand) one bit to the left. The most significant ...

Page 192

Section 2 Instruction Descriptions 2.2.51 (6) ROTL (L) ROTL (ROTate Left) Operation ERd (left rotation) ERd Assembly-Language Format ROTL.L #2, ERd Operand Size Longword Description This instruction rotates the bits in a 32-bit register ERd (destination operand) two bits to ...

Page 193

ROTR (B) ROTR (ROTate Right) Operation Rd (right rotation) Rd Assembly-Language Format ROTR.B Rd Operand Size Byte Description This instruction rotates the bits in an 8-bit register Rd (destination operand) one bit to the right. The least significant ...

Page 194

Section 2 Instruction Descriptions 2.2.52 (2) ROTR (B) ROTR (ROTate Right) Operation Rd (right rotation) Rd Assembly-Language Format ROTR.B #2, Rd Operand Size Byte Description This instruction rotates the bits in an 8-bit register Rd (destination operand) two bits to ...

Page 195

ROTR (W) ROTR (ROTate Right) Operation Rd (right rotation) Rd Assembly-Language Format ROTR.W Rd Operand Size Word Description This instruction rotates the bits in a 16-bit register Rd (destination operand) one bit to the right. The least significant ...

Page 196

Section 2 Instruction Descriptions 2.2.52 (4) ROTR (W) ROTR (ROTate Right) Operation Rd (right rotation) Rd Assembly-Language Format ROTR.W #2, Rd Operand Size Word Description This instruction rotates the bits in a 16-bit register Rd (destination operand) two bits to ...

Page 197

ROTR (L) ROTR (ROTate Right) Operation ERd (right rotation) ERd Assembly-Language Format ROTR.L ERd Operand Size Longword Description This instruction rotates the bits in a 32-bit register ERd (destination operand) one bit to the right. The least significant ...

Page 198

Section 2 Instruction Descriptions 2.2.52 (6) ROTR (L) ROTR (ROTate Right) Operation ERd (right rotation) ERd Assembly-Language Format ROTR.L #2, ERd Operand Size Longword Description This instruction rotates the bits in a 32-bit register ERd (destination operand) two bits to ...

Page 199

ROTXL (B) ROTXL (ROTate with eXtend carry Left) Operation Rd (left rotation through carry flag) Assembly-Language Format ROTXL.B Rd Operand Size Byte Description This instruction rotates the bits in an 8-bit register Rd (destination operand) one bit to ...

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Section 2 Instruction Descriptions 2.2.53 (2) ROTXL (B) ROTXL (ROTate with eXtend carry Left) Operation Rd (left rotation through carry flag) Assembly-Language Format ROTXL.B #2, Rd Operand Size Byte Description This instruction rotates the bits in an 8-bit register Rd ...

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