MC908QL4MDT Freescale Semiconductor, MC908QL4MDT Datasheet
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MC68HC908QL4 Data Sheet M68HC08 Microcontrollers MC68HC908QL4 Rev. 8 04/2010 freescale.com ...
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...
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... Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.freescale.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2006–2010. All rights reserved. ...
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... DC Electrical Characteristics — Updated table notes June, 3.0 Modular sections reworked for clarity. 2004 4 Description MC68HC908QL4 Data Sheet, Rev. 8 Page Number(s) N/A 226 228 236 237 117 140 144 144 156 161 174 196 196 206 227 230 231 Throughout Freescale Semiconductor ...
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... Updated DC injection current specification in the following subsections: April, 8.0 Clarify internal oscillator trim register information. 2010 Freescale Semiconductor Description — Added new section. — Updated entire section for — Added new section. 15.6 TIM During Break Interrupts 16.2.1.2 TIM During Break Interrupts 17 ...
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... Revision History 6 MC68HC908QL4 Data Sheet, Rev. 8 Freescale Semiconductor ...
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... Computer Operating Properly (COP Chapter 7 Central Processor Unit (CPU Chapter 8 External Interrupt (IRQ Chapter 9 Keyboard Interrupt Module (KBI .89 Chapter 10 Low-Voltage Inhibit (LVI .97 Chapter 11 Oscillator Module (OSC .101 Chapter 12 Input/Output Ports (PORTS 111 Chapter 13 System Integration Module (SIM .117 Freescale Semiconductor MC68HC908QL4 Data Sheet, Rev ...
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... List of Chapters Chapter 14 Slave LIN Interface Controller (SLIC) Module . . . . . . . . . . . . . . . . . . . . . . . . 133 Chapter 15 Timer Interface Module (TIM .173 Chapter 16 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Chapter 17 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 Chapter 18 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . 219 8 MC68HC908QL4 Data Sheet, Rev. 8 Freescale Semiconductor ...
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... Conversion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.3.3.1 Initiating Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.3.3.2 Completing Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.3.3.3 Aborting Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.3.3.4 Total Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.3.4 Sources of Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.3.4.1 Sampling Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.3.4.2 Pin Leakage Error 3.3.4.3 Noise-Induced Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Freescale Semiconductor Chapter 1 General Description Chapter 2 Memory Chapter 3 MC68HC908QL4 Data Sheet, Rev ...
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... Keyboard Interrupt Enable Register 4.6.4 Configuration Register 4.6.5 Configuration Register 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10 Chapter 4 Auto Wakeup Module (AWU) Chapter 5 Configuration Register (CONFIG) Chapter 6 Computer Operating Properly (COP) MC68HC908QL4 Data Sheet, Rev. 8 Freescale Semiconductor ...
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... MODE = 8.3.2 MODE = 8.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.6 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Freescale Semiconductor Chapter 7 Central Processor Unit (CPU) Chapter 8 External Interrupt (IRQ) MC68HC908QL4 Data Sheet, Rev. 8 Table of Contents 11 ...
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... Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 11.2 Features 101 11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 11.3.1 Internal Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 11.3.1.1 Oscillator Enable Signal (SIMOSCEN 103 12 Chapter 9 Keyboard Interrupt Module (KBI) Chapter 10 Low-Voltage Inhibit (LVI) Chapter 11 Oscillator Module (OSC) MC68HC908QL4 Data Sheet, Rev. 8 Freescale Semiconductor ...
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... SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 13.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 13.3.2 Clock Start-Up from POR 119 13.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Freescale Semiconductor (INTCLK 103 Chapter 12 Input/Output Ports (PORTS) Chapter 13 System Integration Module (SIM) MC68HC908QL4 Data Sheet, Rev. 8 ...
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... Wakeup from SLIC Wait with CPU in WAIT 137 14.5.7 SLIC Stop 137 14.5.8 Normal and Emulation Mode Operation 138 14.5.9 Special Mode Operation 138 14.5.10 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 14.6 SLIC During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 14 Chapter 14 MC68HC908QL4 Data Sheet, Rev. 8 Freescale Semiconductor ...
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... High-Speed LIN Operation 163 14.9.15 Byte Transfer Mode Operation 165 14.9.16 Oscillator Trimming with SLIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 14.9.17 Digital Receive Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 14.9.17.1 Digital Filter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 14.9.17.2 Digital Filter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Freescale Semiconductor Chapter 15 Timer Interface Module (TIM) MC68HC908QL4 Data Sheet, Rev. 8 Table of Contents 15 ...
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... Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 16.2.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 16.3 Monitor Module (MON 192 16.3.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 16.3.1.1 Normal Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 16.3.1.2 Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 16.3.1.3 Monitor Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 16 Chapter 16 Development Support MC68HC908QL4 Data Sheet, Rev. 8 Freescale Semiconductor ...
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... ADC10 Characteristics 215 17.14 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 17.15 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Ordering Information and Mechanical Specifications 18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 18.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 18.3 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Freescale Semiconductor Chapter 17 Electrical Specifications Chapter 18 MC68HC908QL4 Data Sheet, Rev. 8 Table of Contents 17 ...
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... Table of Contents 18 MC68HC908QL4 Data Sheet, Rev. 8 Freescale Semiconductor ...
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... FLASH security • On-chip random-access memory (RAM) 1. See 17.11 Oscillator Characteristics 2. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Freescale Semiconductor ) DD (1) for internal oscillator specifications MC68HC908QL4 Data Sheet, Rev ...
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... High current sink/source capability – Selectable pullups on all ports (pullup/down on port A), selectable on an individual bit basis – Three-state ability on all port pins • Low-voltage inhibit (LVI) module features: – Software selectable trip point in CONFIG register 20 MC68HC908QL4 Data Sheet, Rev. 8 Freescale Semiconductor ...
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... Binary-coded decimal (BCD) instructions • Optimization for controller applications • Efficient C language support 1.3 MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908QL4. 1.4 Pin Functions Table 1-1 provides a description of the pin functions. Freescale Semiconductor MC68HC908QL4 Data Sheet, Rev. 8 MCU Block Diagram 21 ...
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... MODULE AUTO WAKEUP MODULE LOW-VOLTAGE INHIBIT 2-CHANNEL 16-BIT TIMER MODULE COP MODULE 6-CHANNEL 10-BIT ADC SLAVE LIN INTERFACE CONTROLLER DEVELOPMENT SUPPORT MONITOR ROM BREAK MODULE 1 16 PTB4/SLCRx 2 15 PTB5/SLCTx PTB6 3 14 TSSOP PTB7 SS PTB1 PTB2/AD4 7 10 PTB3/AD5 8 9 PTB0/TCH0 Freescale Semiconductor ...
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... PTB4 — General purpose I/O port PTB4 SLCRx — SLC receive input PTB5 — General purpose I/O port PTB5 SLCTx — SLC transmit output PTB6, PTB7 General-purpose I/O port Freescale Semiconductor Table 1-1. Pin Functions Description MC68HC908QL4 Data Sheet, Rev. 8 Pin Functions Input/Output Power Power ...
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... RST → KBI3 → PTA3 (1) OSC2 → AD2 → KBI4 → PTA4 OSC1 → AD3 → KBI5 → PTA5 (1) TCH0 → PTB0 PTB1 AD4 → PTB2 (1) (1) AD5 → PTB3 SLCRx → PTB4 SLCTx → PTB5 MC68HC908QL4 Data Sheet, Rev. 8 (2) Freescale Semiconductor ...
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... Registers between $0100 and $FFFF require non-direct page addressing modes. See Chapter 7 Central Processor Unit (CPU) addressing modes. Freescale Semiconductor MC68HC908QL4 Data Sheet, Rev. 8 Figure 2-1, Figure ...
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... BYTES AUXILIARY ROM 674 BYTES UNIMPLEMENTED 49120 BYTES FLASH MEMORY 4096 BYTES MISCELLANEOUS REGISTERS 16 BYTES UNIMPLEMENTED 16 BYTES MONITOR ROM 350 BYTES UNIMPLEMENTED 64 BYTES MISCELLANEOUS REGISTERS 4 BYTES UNIMPLEMENTED 14 BYTES USER VECTORS 48 BYTES Figure 2-1. Memory Map MC68HC908QL4 Data Sheet, Rev. 8 Freescale Semiconductor ...
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... Read: Keyboard Status and $001A Control Register (KBSCR) Write: See page 94. Reset: Read: Keyboard Interrupt $001B Enable Register (KBIER) Write: See page 95. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit AWUL PTA5 PTA4 PTB7 PTB6 PTB5 ...
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... KBIP2 KBIP1 KBIP0 IRQF 0 IMASK MODE ACK OSCENIN RSTEN STOP ( LVITRIP SSREC STOP COPD ( PS2 PS1 PS0 Bit 11 Bit 10 Bit 9 Bit Bit 3 Bit 2 Bit 1 Bit Bit 11 Bit 10 Bit 9 Bit Bit 3 Bit 2 Bit 1 Bit ELS0B ELS0A TOV0 CH0MAX Reserved U = Unaffected Freescale Semiconductor ...
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... ADC10 Status and Control $003C Register (ADSCR) Write: See page 52. Reset: Read: ADC10 Data Register High $003D (ADRH) Write: See page 54. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit Bit 15 Bit 14 Bit 13 Bit 12 Indeterminate after reset Bit 7 Bit 6 Bit 5 Bit 4 ...
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... TXGO CHKMOD DLC5 DLC4 Unimplemented R MC68HC908QL4 Data Sheet, Rev Bit 0 AD3 AD2 AD1 AD0 MODE1 MODE0 ADLSMP ADACKEN WAKETX TXABRT IMSG SLCIE SLCWCM BTM SLCE SLCF BT11 BT10 BT9 BT8 BT3 BT2 BT1 DLC3 DLC2 DLC1 DLC0 Reserved U = Unaffected Freescale Semiconductor ...
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... Write: See page 191. Reset: Read: SIM Reset Status Register $FE01 (SRSR) Write: See page 131. POR: Read: Break Auxiliary $FE02 Register (BRKAR) Write: See page 191. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit ...
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... BPR7 BPR6 BPR5 BPR4 Unaffected by reset = Unimplemented R MC68HC908QL4 Data Sheet, Rev Bit IF2 IF1 IF10 IF9 IF8 IF7 IF18 IF17 IF16 IF15 HVEN MASS ERASE PGM Bit 11 Bit 10 Bit 9 Bit Bit 3 Bit 2 Bit 1 Bit BPR3 BPR2 BPR1 = Reserved U = Unaffected Freescale Semiconductor ...
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... Figure 2-2. Control, Status, and Data Registers (Sheet Vector Priority Vector IF22–IF16 Lowest IF15 IF14 IF13 IF12 IF11 IF10 Highest Freescale Semiconductor Bit TRIM7 TRIM6 TRIM5 TRIM4 Resets to factory programmed value LOW BYTE OF RESET VECTOR WRITING CLEARS COP COUNTER (ANY VALUE) = Unimplemented Table 2-1 ...
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... FLASH contents security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. 34 ;point one past RAM ;SP<-(H:X-1) supply. The program and erase operations are DD NOTE (1) MC68HC908QL4 Data Sheet, Rev. 8 Freescale Semiconductor ...
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... Erase operation unselected PGM — Program Control Bit This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal set the same time Program operation selected 0 = Program operation unselected Freescale Semiconductor ...
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... FLASH memory. While these operations must be performed in the order as shown, other unrelated operations may occur between the steps. A page erase of the vector page will erase the internal oscillator trim value at $FFC0. 36 NOTE NOTE CAUTION MC68HC908QL4 Data Sheet, Rev. 8 Freescale Semiconductor ...
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... A mass erase will erase the internal oscillator trim value at $FFC0. 1. When in monitor mode, with security sequence failed (see instead of any FLASH address. Freescale Semiconductor (1) within the FLASH memory address range. NOTE NOTE CAUTION 16 ...
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... Characteristics. 1. The time between each FLASH address change, or the time between the last FLASH address programmed to clearing PGM bit, must not exceed the maximum programming time NOTE (1) . NOTE NOTE maximum, see PROG maximum. PROG MC68HC908QL4 Data Sheet, Rev. 8 17.15 Freescale Semiconductor ...
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... PROG This row program algorithm assumes the row programmed is initially erased. Figure 2-4. FLASH Programming Flowchart Freescale Semiconductor 1 SET PGM BIT 2 READ THE FLASH BLOCK PROTECT REGISTER 3 WRITE ANY DATA TO ANY FLASH ADDRESS ...
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... Register. Once the FLBPR is programmed with a value other than , present on the IRQ pin. This voltage also TST BPR6 BPR5 BPR4 BPR3 Unaffected by reset. Initial value from factory is $FF. and Table 2-2. MC68HC908QL4 Data Sheet, Rev Bit 0 BPR2 BPR1 BPR0 Freescale Semiconductor ...
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... The end address of the protected range is always $FFFF. Freescale Semiconductor 16-BIT MEMORY ADDRESS FLBPR VALUE 1 1 Start of Address of Protect Range The entire FLASH memory is protected. $EE40 (1110 1110 0100 0000) ...
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... Memory 42 MC68HC908QL4 Data Sheet, Rev. 8 Freescale Semiconductor ...
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... REFH a 8-bit representation. If ADVIN is equal to or less than V Input voltages between V REFH Input voltage must not exceed the analog supply voltages. Freescale Semiconductor REFL and V are straight-line linear conversions. REFL NOTE MC68HC908QL4 Data Sheet, Rev ...
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... INTERNAL OSC INTERNAL CLOCK SOURCE 4, 8, 12.8, or 25.6 MHz KEYBOARD INTERRUPT MODULE EXTERNAL INTERRUPT MODULE AUTO WAKEUP MODULE LOW-VOLTAGE INHIBIT 2-CHANNEL 16-BIT TIMER MODULE COP MODULE 6-CHANNEL 10-BIT ADC SLAVE LIN INTERFACE CONTROLLER DEVELOPMENT SUPPORT MONITOR ROM BREAK MODULE Freescale Semiconductor ...
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... This clock is selected when ADICLK and ACLKEN are both low. • The bus clock — This clock source is equal to the bus frequency. This clock is selected when ADICLK is high and ACLKEN is low. Freescale Semiconductor ADCLK ADCK CLOCK CONTROL SEQUENCER ...
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... A write to ADCSC occurs (the current conversion will be aborted and a new conversion will be initiated, if ADCH are not all 1s). • A write to ADCLK occurs. • The MCU is reset. • The MCU enters stop mode with ACLK not enabled. 46 MC68HC908QL4 Data Sheet, Rev. 8 Freescale Semiconductor ...
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... MHz, then the conversion time for a single 10-bit conversion is: Maximum Conversion time = Number of bus cycles = 11.25 μ MHz = 45 cycles The ADCK frequency must be between f maximum to meet A/D specifications. Freescale Semiconductor ACLKEN 0 1 ≥ ...
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... DDA SSA at a quiet point in the ground plane. SS noise but will increase effective conversion time DD MC68HC908QL4 Data Sheet, Rev kept below high (4096*I ) for less than ADVIN Leak or V (if available). This will REFL SSA , one-time error. LSB Freescale Semiconductor ...
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... Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code for a higher input voltage. • Missing codes are those which are never converted for any input value. In 8-bit or 10-bit mode, the ADC10 is guaranteed to be monotonic and to have no missing codes. Freescale Semiconductor –V ...
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... To protect status bits during the break state, write BCFE. With BCFE cleared (its default state), software can read and write registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the 50 sheet. MC68HC908QL4 Data Sheet, Rev. 8 Freescale Semiconductor ...
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... In some packages, REFL V is connected internally to V REFL potential There will be a brief current associated with V SSA Freescale Semiconductor ) DDA as its power pin. In some packages, V DDA pin to the same voltage potential as V DDA for good results. ...
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... The ADC10 will continue to convert until the MCU enters reset, the MCU enters stop mode (if ACLKEN is clear), ADCLK is written, or until ADCSC is written again. If stop is entered 52 pin to the same potential as V REFL AIEN ADCO ADCH4 ADCH3 MC68HC908QL4 Data Sheet, Rev the single point SSA 2 1 Bit 0 ADCH2 ADCH1 ADCH0 Freescale Semiconductor . SSA ...
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... ADCH4 ADCH3 any unused or reserved channels are selected, the resulting conversion will be unknown. 2. Requires LVI to be powered (LVIPWRD = 0, in CONFIG1) Freescale Semiconductor 3-2. The successive approximation converter subsystem is turned off Table 3-2. Input Channel Select ADCH2 ADCH1 ADCH0 Continuing through ...
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... In 8-bit mode, there is no interlocking with ADRH. Bit 7 Read: AD7 Write: Reset Unimplemented Figure 3-6. ADC10 Data Register Low (ADRL AD6 AD5 AD4 AD3 MC68HC908QL4 Data Sheet, Rev Bit Bit 0 0 AD9 AD8 Bit 0 AD2 AD1 AD0 Freescale Semiconductor ...
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... LSB Reset returns 8-bit mode 8-bit, right-justified, ADCSC software triggered mode enabled 01 = 10-bit, right-justified, ADCSC software triggered mode enabled 10 = Reserved 11 = 10-bit, right-justified, hardware triggered mode enabled Freescale Semiconductor ADIV0 ADICLK MODE1 0 ...
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... MHz if ADLPC is clear, and between 0.5 MHz and 1 MHz if ADLPC is set The asynchronous clock is selected as the input clock source (the clock generator is only enabled during the conversion ADICLK specifies the input clock source and conversions will not continue in stop mode 56 MC68HC908QL4 Data Sheet, Rev. 8 Freescale Semiconductor ...
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... Exit from low-power stop mode without external signals • Selectable timeout periods • Dedicated low-power internal oscillator separate from the main system clock sources • Option to allow bus clock source to run the AWU if enabled in STOP Freescale Semiconductor AUTOWUGEN DIV 2 SHORT DIV 2 ...
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... AWU Latch (AWUL) — The AWUL bit is set when the AWU counter overflows. The auto wakeup interrupt mask bit, AWUIE, is used to enable or disable AWU interrupt requests. The AWU shares its interrupt with the KBI vector. 58 4-1. MC68HC908QL4 Data Sheet, Rev. 8 Figure 4-1 applied Figure 4-1) has no effect on AWUL Freescale Semiconductor ...
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... There is no PTA6 port or any of the associated bits such as PTA6 data direction or pullup bits Auto wakeup interrupt request is pending 0 = Auto wakeup interrupt request is not pending PTA5–PTA0 bits are not used in conjuction with the auto wakeup feature. To see a description of these bits, see Freescale Semiconductor PTA5 ...
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... Bit 7 Read: 0 AWUIE Write: Reset Unimplemented Figure 4-4. Keyboard Interrupt Enable Register (KBIER KEYF NOTE 9.8.1 Keyboard Status and Control Register KBIE5 KBIE4 KBIE3 MC68HC908QL4 Data Sheet, Rev Bit 0 0 IMASKK MODEK ACKK Bit 0 KBIE2 KBIE1 KBIE0 Freescale Semiconductor ...
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... The configuration register 1 (CONFIG1), is used to select the period for the AWU. The timeout will be based on the COPRS bit along with the clock source for the AWU. Bit 7 Read: COPRS Write: 0 Reset: POR Unaffected Figure 4-6. Configuration Register 1 (CONFIG1) Freescale Semiconductor NOTE 9.8.2 Keyboard Interrupt Enable ...
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... Stop mode recovery after 32 BUSCLKX4 cycles 0 = Stop mode recovery after 4096 BUSCLKX4 cycles LVISTOP, LVIRST, LVIPWRD, LVITRIP, and COPD bits are not used in conjuction with the auto wakeup feature. To see a description of these bits, see Chapter 5 Configuration Register (CONFIG) 62 NOTE MC68HC908QL4 Data Sheet, Rev. 8 Freescale Semiconductor ...
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... The CONFIG registers are one-time writable by the user after each reset. Upon a reset, the CONFIG registers default to predetermined settings as shown in Figure 5-1 Bit 7 6 Read: IRQPUD IRQEN Write: Reset POR Reserved R Figure 5-1. Configuration Register 2 (CONFIG2) Freescale Semiconductor NOTE and Figure 5- Unaffected MC68HC908QL4 Data Sheet, Rev. 8 ...
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... LVI disabled during stop mode LVIRSTD — LVI Reset Disable Bit LVIRSTD disables the reset signal from the LVI module LVI module resets disabled 0 = LVI module resets enabled 64 DD NOTE LVIRSTD LVIPWRD LVITRIP MC68HC908QL4 Data Sheet, Rev Bit 0 SSREC STOP COPD Freescale Semiconductor ...
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... STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD — COP Disable Bit COPD disables the COP module COP module disabled 0 = COP module enabled Freescale Semiconductor for the LVI’s voltage trip points for each of the modes. DD NOTE NOTE MC68HC908QL4 Data Sheet, Rev. 8 ...
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... Configuration Register (CONFIG) 66 MC68HC908QL4 Data Sheet, Rev. 8 Freescale Semiconductor ...
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... COPEN (FROM SIM) COPD (FROM CONFIG1) RESET COPCTL WRITE COP RATE SELECT (COPRS FROM CONFIG1) 1. See Chapter 13 System Integration Module (SIM) Freescale Semiconductor SIM MODULE 12-BIT SIM COUNTER COP CLOCK COP MODULE 6-BIT COP COUNTER CLEAR COP COUNTER for more details. ...
Page 68
... The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register (CONFIG). See Chapter 5 Configuration Register 68 NOTE NOTE Figure 6-1. Figure (CONFIG). MC68HC908QL4 Data Sheet, Rev. 8 13.8.1 SIM Reset Status Register. 6-2) clears the COP counter and Freescale Semiconductor ...
Page 69
... COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector. Address: $FFFF Bit 7 Read: Write: Reset: Figure 6-2. COP Control Register (COPCTL) Freescale Semiconductor (CONFIG). is present on the IRQ pin. TST ...
Page 70
... Computer Operating Properly (COP) 70 MC68HC908QL4 Data Sheet, Rev. 8 Freescale Semiconductor ...
Page 71
... Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes 7.3 CPU Registers Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map. Freescale Semiconductor MC68HC908QL4 Data Sheet, Rev ...
Page 72
... CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 7-1. CPU Registers Unaffected by reset Figure 7-2. Accumulator ( Figure 7-3. Index Register (H:X) MC68HC908QL4 Data Sheet, Rev Bit 0 Bit Freescale Semiconductor ...
Page 73
... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit Read: Write: Reset: Freescale Semiconductor ...
Page 74
... N — Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result Negative result 0 = Non-negative result NOTE MC68HC908QL4 Data Sheet, Rev Bit Freescale Semiconductor ...
Page 75
... CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. Freescale Semiconductor MC68HC908QL4 Data Sheet, Rev. 8 Arithmetic/Logic Unit (ALU) ...
Page 76
... REL 27 rr – – – – – – REL – – – – – – REL 28 rr – – – – – – REL 29 rr – – – – – – REL 22 rr Freescale Semiconductor ...
Page 77
... Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel CLC Clear Carry Bit CLI Clear Interrupt Mask Freescale Semiconductor Description PC ← (PC rel ? ( ← (PC rel ? IRQ = 1 PC ← (PC rel ? IRQ = 0 (A) & (M) ⊕ PC ← (PC rel ? ( – – – – – – REL PC ← ...
Page 78
... INH 4A INH 5A – – – IX1 SP1 9E6A ff – – – – INH 52 IMM A8 ii DIR B8 dd EXT IX2 – – – IX1 SP1 9EE8 ff SP2 9ED8 ee ff DIR 3C dd INH 4C INH 5C – – – IX1 SP1 9E6C ff Freescale Semiconductor ...
Page 79
... ORA opr,X ORA ,X ORA opr,SP ORA opr,SP PSHA Push A onto Stack PSHH Push H onto Stack PSHX Push X onto Stack Freescale Semiconductor Description PC ← Jump Address PC ← (PC Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – ← Unconditional Address A ← (M) H:X ← (M ← (M) ...
Page 80
... DIR 35 dd – – 0 – – – INH 8E DIR BF dd EXT IX2 – – – IX1 SP1 9EEF ff SP2 9EDF ee ff IMM A0 ii DIR B0 dd EXT IX2 – – IX1 SP1 9EE0 ff SP2 9ED0 ee ff Freescale Semiconductor ...
Page 81
... M Memory location N Negative bit 7.8 Opcode Map See Table 7-2. Freescale Semiconductor Description PC ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – ← 1 PCH ← Interrupt Vector High Byte PCL ← ...
Page 82
Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...
Page 83
... The external IRQ pin is falling edge sensitive out of reset and is software-configurable to be either falling edge or falling edge and low level sensitive. The MODE bit in INTSCR controls the triggering sensitivity of the IRQ pin. Freescale Semiconductor for more information on enabling the IRQ pin. MC68HC908QL4 Data Sheet, Rev. 8 ...
Page 84
... INTERNAL OSC INTERNAL CLOCK SOURCE 4, 8, 12.8, or 25.6 MHz KEYBOARD INTERRUPT MODULE EXTERNAL INTERRUPT MODULE AUTO WAKEUP MODULE LOW-VOLTAGE INHIBIT 2-CHANNEL 16-BIT TIMER MODULE COP MODULE 6-CHANNEL 10-BIT ADC SLAVE LIN INTERFACE CONTROLLER DEVELOPMENT SUPPORT MONITOR ROM BREAK MODULE Freescale Semiconductor ...
Page 85
... The IRQF bit in INTSCR can be read to check for pending interrupts. The IRQF bit is not affected by IMASK, which makes it useful in applications where polling is preferred. When using the level-sensitive interrupt trigger, avoid false IRQ interrupts by masking interrupt requests in the interrupt routine. Freescale Semiconductor V DD CLR ...
Page 86
... I/O Signals The IRQ module does not share its pin with any module on this MCU. 8.7.1 IRQ Input Pins (IRQ) The IRQ pin provides a maskable external interrupt source. The IRQ pin contains an internal pullup device. 86 MC68HC908QL4 Data Sheet, Rev. 8 sheet. Freescale Semiconductor ...
Page 87
... Writing this read/write bit disables the IRQ interrupt request IRQ interrupt request disabled 0 = IRQ interrupt request enabled MODE — IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ pin IRQ interrupt request on falling edges and low levels 0 = IRQ interrupt request on falling edges only Freescale Semiconductor ...
Page 88
... External Interrupt (IRQ) 88 MC68HC908QL4 Data Sheet, Rev. 8 Freescale Semiconductor ...
Page 89
... PTAPUEx see Pullup/Down Enable Register. On falling edge or low level detection, a pullup device is configured. On rising edge or high level detection, a pulldown device is configured. Freescale Semiconductor MC68HC908QL4 Data Sheet, Rev. 8 Figure 9-1 for port location Figure 9-2 ...
Page 90
... INTERNAL OSC INTERNAL CLOCK SOURCE 4, 8, 12.8, or 25.6 MHz KEYBOARD INTERRUPT MODULE EXTERNAL INTERRUPT MODULE AUTO WAKEUP MODULE LOW-VOLTAGE INHIBIT 2-CHANNEL 16-BIT TIMER MODULE COP MODULE 6-CHANNEL 10-BIT ADC SLAVE LIN INTERFACE CONTROLLER DEVELOPMENT SUPPORT MONITOR ROM BREAK MODULE Freescale Semiconductor ...
Page 91
... KBSCR. The ACKK bit is useful in applications that poll the keyboard interrupt inputs and require software to clear the KBI latch. Writing to ACKK prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions Freescale Semiconductor V DD ...
Page 92
... Keyboard flag (KEYF) — The KEYF bit is set when any enabled KBI pin is asserted based on the KBI mode and pin polarity. The keyboard interrupt mask bit, IMASKK, is used to enable or disable KBI interrupt requests. 92 NOTE MC68HC908QL4 Data Sheet, Rev. 8 Freescale Semiconductor ...
Page 93
... KBSCR (keyboard interrupt status and control register) • KBIER (keyboard interrupt enable register) • KBIPR (keyboard interrupt polarity register) Freescale Semiconductor 12.3.3 Port A Input Pullup/Down Enable MC68HC908QL4 Data Sheet, Rev. 8 Low-Power Modes Figure 9-1 for the port pins that Register. The ...
Page 94
... Keyboard interrupt requests enabled MODEK — Keyboard Triggering Sensitivity Bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins Keyboard interrupt requests on edge and level 0 = Keyboard interrupt requests on edge only KEYF MC68HC908QL4 Data Sheet, Rev Bit 0 0 IMASKK MODEK ACKK Freescale Semiconductor ...
Page 95
... Each of these read/write bits enables the polarity of the keyboard interrupt detection Keyboard polarity is high level and/or rising edge. Port pulldown is enabled if the corresponding PTAPUE bit is set Keyboard polarity is low level and/or falling edge. Port pullup is enabled if the corresponding PTAPUE bit is set. Freescale Semiconductor ...
Page 96
... Keyboard Interrupt Module (KBI) 96 MC68HC908QL4 Data Sheet, Rev. 8 Freescale Semiconductor ...
Page 97
... LVI module. LVISTOP, LVIPWRD, LVITRIP, and LVIRSTD are user selectable options found in the configuration register FROM CONFIGURATION REGISTER LOW V DD DETECTOR LVITRIP FROM CONFIGURATION REGISTER Freescale Semiconductor Chapter 5 Configuration Register STOP INSTRUCTION FROM CONFIGURATION REGISTER LVIRSTD LVIPWRD > TRIPR ≤ ...
Page 98
... DD is greater than V by the typical hysteresis voltage, V TRIPR TRIPF NOTE Chapter 17 Electrical MC68HC908QL4 Data Sheet, Rev. 8 operating range. The actual DD and 17.8 3.3-V DC Electrical must See Chapter 13 System TRIPR ) for the higher V TRIPF by polling DD Freescale Semiconductor HYS ...
Page 99
... The LVI status register (LVISR) contains a status bit that is useful when the LVI is enabled and LVI reset is disabled. Bit 7 Read: LVIOUT Write: Reset Unimplemented Figure 10-2. LVI Status Register (LVISR) LVIOUT — LVI Output Bit This read-only flag becomes set when the V when V voltage rises above Freescale Semiconductor voltage falls below the V DD ...
Page 100
... Low-Voltage Inhibit (LVI) 100 MC68HC908QL4 Data Sheet, Rev. 8 Freescale Semiconductor ...
Page 101
... The oscillator contains these major subsystems: • Internal oscillator circuit • Internal or external clock switch control • External clock circuit • External crystal circuit • External RC clock circuit Freescale Semiconductor for information on PTAPUEN register. MC68HC908QL4 Data Sheet, Rev. 8 Figure 11-1 for port 101 ...
Page 102
... INTERNAL OSC INTERNAL CLOCK SOURCE 4, 8, 12.8, or 25.6 MHz KEYBOARD INTERRUPT MODULE EXTERNAL INTERRUPT MODULE AUTO WAKEUP MODULE LOW-VOLTAGE INHIBIT 2-CHANNEL 16-BIT TIMER MODULE COP MODULE 6-CHANNEL 10-BIT ADC SLAVE LIN INTERFACE CONTROLLER DEVELOPMENT SUPPORT MONITOR ROM BREAK MODULE Freescale Semiconductor ...
Page 103
... MHz, 3.2 MHz, 2.0 MHz, or 1.0 MHz respectively. The bus clock is software selectable and defaults to the 3.2-MHz bus out of reset. Users can increase the bus frequency based on the voltage range of their application. Freescale Semiconductor Figure 11-2 shows only the logical relation of XTALCLK to OSC1 ...
Page 104
... BUSCLKX4 and also divided by two to create BUSCLKX2. In this configuration, the OSC2 pin cannot output BUSCLKX4. The OSC2EN bit will be forced clear to enable alternative functions on the pin. 104 11.8.1 Oscillator Status and Control MC68HC908QL4 Data Sheet, Rev. 8 Register. Freescale Semiconductor ...
Page 105
... Refer to the oscillator characteristics table in the electricals section for more information. SIMOSCEN (internal signal) OR OSCENINSTOP (bit located in configuration register)) MCU OSC1 Figure 11-2. XTAL Oscillator External Connections Freescale Semiconductor NOTE ) is included in the diagram to follow strict Pierce S BUSCLKX4 BUSCLKX2 XTALCLK ÷ 2 ...
Page 106
... OSC2- available for alternative pin function See the electricals section for component value. MC68HC908QL4 Data Sheet, Rev provide a clock source with EXT 11-3. value must have a tolerance of EXT . RCCLK OSCOPT = EXTERNAL RC SELECTED BUSCLKX2 BUSCLKX4 ÷ 2 ALTERNATIVE PIN FUNCTION OSC2EN Freescale Semiconductor ...
Page 107
... RC, the OSC2 pin can be used to output BUSCLKX4. Option XTAL oscillator External clock Internal oscillator or RC oscillator Freescale Semiconductor Table 11-1. OSC2 Pin Function OSC2 Pin Function Inverting OSC1 General-purpose I/O or alternative pin function Controlled by OSC2EN bit OSC2EN = 0: General-purpose I/O or alternative pin function OSC2EN = 1: BUSCLKX4 output MC68HC908QL4 Data Sheet, Rev ...
Page 108
... External oscillator clock 0 External RC 1 External crystal (range selected using ECFSx bits) ICFS0 Internal Clock Frequency 0 4.0 MHz 1 8.0 MHz 0 12.8 MHz — default reset condition 1 25.6 MHz MC68HC908QL4 Data Sheet, Rev Bit 0 ECGST ECFS0 ECGON 11.3.2.2 Internal to External Freescale Semiconductor ...
Page 109
... The oscillator period is based on the oscillator frequency selected by the ICFS bits in OSCSC. Applications using the internal oscillator should copy the internal oscillator trim value at location $FFC0 into this register to trim the clock source. Freescale Semiconductor ECFS0 External Crystal Frequency 0 8 MHz – ...
Page 110
... Oscillator Module (OSC) 110 MC68HC908QL4 Data Sheet, Rev. 8 Freescale Semiconductor ...
Page 111
... In this case, the BIH and BIL instructions can be used to read the logic level on the PTA2 pin. When the IRQ function is disabled, these instructions will behave as if the PTA2 pin is a logic 1. However, reading bit 2 of PTA will read the actual logic level on the pin. Freescale Semiconductor ...
Page 112
... PTA5 PTA4 PTA3 Unaffected by reset = Unimplemented Figure 12-1. Port A Data Register (PTA) Chapter 4 Auto Wakeup Module DDRA5 DDRA4 DDRA3 Unimplemented NOTE MC68HC908QL4 Data Sheet, Rev Bit 0 PTA2 PTA1 PTA0 (AWU)). There is no PTA6 2 1 Bit 0 0 DDRA1 DDRA0 Freescale Semiconductor ...
Page 113
... This bit has no effect for the XTAL or external oscillator options OSC2 pin outputs the internal or RC oscillator clock (BUSCLKX4 OSC2 pin configured for PTA4 I/O, having all the interrupt and pullup/down functions Freescale Semiconductor DDRAx PTAx Figure 12-3. Port A I/O Circuit ...
Page 114
... PTB6 PTB5 PTB4 PTB3 Unaffected by reset Figure 12-5. Port B Data Register (PTB) MC68HC908QL4 Data Sheet, Rev. 8 Accesses to PTA Read Write (3) Pin PTA5–PTA0 (3) Pin PTA5–PTA0 (5) PTA5–PTA0 PTA5–PTA0 Chapter 3 Analog-to-Digital Chapter 14 Slave 2 1 Bit 0 PTB2 PTB1 PTB0 Freescale Semiconductor ...
Page 115
... WRITE DDRB WRITE PTB READ PTB When DDRBx reading PTB reads the PTBx data latch. When DDRBx reading PTB reads the logic level on the PTBx pin. The data latch can always be written, regardless of the state of its data direction bit. Freescale Semiconductor DDRB5 ...
Page 116
... PTBPUE5 PTBPUE4 PTBPUE3 Table 12-2. Port B Pin Functions Accesses to DDRB I/O Pin Mode Read/Write (2) DDRB7–DDRB0 Input, Hi-Z Output DDRB7–DDRB0 MC68HC908QL4 Data Sheet, Rev Bit 0 PTBPUE2 PTBPUE2 PTBPUE0 Accesses to PTB Read Write (3) Pin PTB7–PTB0 Pin PTB7–PTB0 Freescale Semiconductor ...
Page 117
... BUSCLKX2 Address bus Data bus PORRST IRST R/W Freescale Semiconductor Figure Table 13-1. Signal Name Conventions Description Buffered clock from the internal XTAL oscillator circuit. The BUSCLKX4 frequency divided by two. This signal is again divided by two in the SIM to generate the internal bus clocks (bus clock = BUSCLKX4 ÷ ...
Page 118
... BUSCLKX4 (FROM OSCILLATOR) BUSCLKX2 (FROM OSCILLATOR) INTERNAL CLOCKS ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP TIMEOUT (FROM COP MODULE) LVI RESET (FROM LVI MODULE) FORCED MON MODE ENTRY (FROM MENRST MODULE) INTERRUPT SOURCES CPU INTERFACE Freescale Semiconductor ...
Page 119
... In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. Freescale Semiconductor Chapter 5 Configuration Register FROM ...
Page 120
... LVI, or POR (see Figure 13-5). 120 13.5 SIM Counter), but an external reset does not. Each of shows the relative timing. The RST pin function is only available VECT H VECT L Figure 13-3. External Reset Timing NOTE 13-4. MC68HC908QL4 Data Sheet, Rev. 8 13.8 SIM Registers. Freescale Semiconductor ...
Page 121
... Internal clocks to the CPU and modules are held inactive for 4096 BUSCLKX4 cycles to allow stabilization of the oscillator. • The POR bit of the SIM reset status register (SRSR) is set. See Figure 13-6. Freescale Semiconductor RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES Figure 13-4. Internal Reset Timing ILLEGAL ADDRESS RST ILLEGAL OPCODE RST ...
Page 122
... CYCLES CYCLES (RST PIN IS A GENERAL-PURPOSE INPUT AFTER A POR) Figure 13-6. POR Recovery Figure 2-1. Memory Map voltage falls to the LVI trip voltage V DD MC68HC908QL4 Data Sheet, Rev. 8 $FFFE $FFFF for memory ranges. . The LVI TRIPF Freescale Semiconductor ...
Page 123
... Break interrupts 13.6.1 Interrupts An interrupt temporarily changes the sequence of program execution to respond to a particular event. Figure 13-7 flow charts the handling of system interrupts. Freescale Semiconductor rises above V DD 13.7.2 Stop Mode 13.4.2 Active Resets from Internal Sources MC68HC908QL4 Data Sheet, Rev. 8 SIM Counter ...
Page 124
... I BIT SET? NO YES IRQ INTERRUPT? NO YES TIMER INTERRUPT? NO LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI YES INSTRUCTION? NO RTI YES UNSTACK CPU REGISTERS INSTRUCTION? NO Figure 13-7. Interrupt Processing MC68HC908QL4 Data Sheet, Rev. 8 STACK CPU REGISTERS SET I BIT EXECUTE INSTRUCTION Freescale Semiconductor ...
Page 125
... MODULE INTERRUPT I BIT ADDRESS BUS DUMMY SP DATA BUS DUMMY R/W MODULE INTERRUPT I BIT ADDRESS BUS SP – 4 DATA BUS R/W Freescale Semiconductor shows interrupt recovery timing. SP – – – – – 1[7:0] PC – 1[15: Figure 13-8 Interrupt Entry SP – – – 1 CCR ...
Page 126
... A software interrupt pushes PC onto the stack. A software interrupt does not push PC – hardware interrupt does. 126 NOTE CLI LDA #$FF PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI . Interrupt Recognition Example NOTE MC68HC908QL4 Data Sheet, Rev. 8 BACKGROUND ROUTINE Freescale Semiconductor ...
Page 127
... Reserved Figure 13-12. Interrupt Status Register 2 (INT2) IF7–I 14 — Interrupt Flags F This flag indicates the presence of interrupt requests from the sources shown Interrupt request present interrupt request present Freescale Semiconductor Table 13-3. Interrupt Sources Flag Mask — — — — ...
Page 128
... Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur. 128 IF21 IF20 IF19 IF18 Support.) The SIM puts the CPU into the break MC68HC908QL4 Data Sheet, Rev Bit 0 IF17 IF16 IF15 Table 13-3. Freescale Semiconductor ...
Page 129
... RST BUSCLKX4 1. RST is only available if the RSTEN bit in the CONFIG1 register is set. Figure 13-16. Wait Recovery from Internal Reset Freescale Semiconductor WAIT ADDR + 1 SAME PREVIOUS DATA NEXT OPCODE Figure 13-14. Wait Mode Entry Timing show the timing for wait recovery. ...
Page 130
... Figure 13-17 NOTE STOP ADDR + 1 SAME PREVIOUS DATA NEXT OPCODE Figure 13-17. Stop Mode Entry Timing STOP RECOVERY PERIOD STOP +1 STOP + 2 STOP + 2 MC68HC908QL4 Data Sheet, Rev. 8 shows stop mode entry timing and SAME SAME SAME SP SP – – – 3 Freescale Semiconductor ...
Page 131
... MODRST — Monitor Mode Entry Module Reset bit 1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after POR while IRQB = POR or read of SRSR LVI — Low Voltage Inhibit Reset bit 1 = Last reset caused by LVI circuit 0 = POR or read of SRSR Freescale Semiconductor PIN COP ...
Page 132
... This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break 132 MC68HC908QL4 Data Sheet, Rev Bit Freescale Semiconductor ...
Page 133
... Switchable UART-like byte transfer mode for processing bytes one at a time without LIN message framing constraints • Enhanced checksum (includes ID) generation and verification 1. Maximum bit rate of SLIC module dependent upon frequency of SLIC input clock. Freescale Semiconductor (1) MC68HC908QL4 Data Sheet, Rev. 8 Figure 14-1 for port ...
Page 134
... INTERNAL OSC INTERNAL CLOCK SOURCE 4, 8, 12.8, or 25.6 MHz KEYBOARD INTERRUPT MODULE EXTERNAL INTERRUPT MODULE AUTO WAKEUP MODULE LOW-VOLTAGE INHIBIT 2-CHANNEL 16-BIT TIMER MODULE COP MODULE 6-CHANNEL 10-BIT ADC SLAVE LIN INTERFACE CONTROLLER DEVELOPMENT SUPPORT MONITOR ROM BREAK MODULE Freescale Semiconductor ...
Page 135
... STATUS REGISTERS CONTROL REGISTERS MESSAGE BUFFER — 9 BYTES SLCD7, SLCD6, SLCD5, SLCD4 SLCD3, SLCD2, SLCD1, SLCD0 BUS CLOCK Figure 14-2. SLIC Module Block Diagram Freescale Semiconductor LSVR AND LINIF SLCSVR CONTROL LIN PROTOCOL STATE MACHINE SLCID SHADOW REGISTER 1 BYTE SLIC CLOCK ...
Page 136
... MCU reset source is asserted. To prevent the SLIC from MC68HC908QL4 Data Sheet, Rev > V (MIN) AND ANY DD DD MCU RESET SOURCE ASSERTED NO MCU RESET SOURCE ASSERTED INITREQ = 0; (INITACK = 0) SLCE SET IN SLCC2 REGISTER NETWORK ACTIVITY OR OTHER MCU WAKEUP SLIC WAIT drops below DD rises above DD Freescale Semiconductor ...
Page 137
... SLIC stop mode and generate an unmaskable interrupt of the CPU. This wakeup interrupt state is reflected in the SLCSV, encoded as the highest priority interrupt. This interrupt can be cleared by the CPU with a read of the SLCSV and clearing of the SLCF interrupt flag. Depending upon which low-power mode Freescale Semiconductor MC68HC908QL4 Data Sheet, Rev. 8 Modes of Operation ...
Page 138
... SLIC module does while in a low-power mode can be found in 14.6 SLIC During Break Interrupts The BCFE bit in the BSCR register has no affect on the SLIC module. Therefore the SLIC modules status bits cannot be protected during break. 138 NOTE 14.5 Modes of MC68HC908QL4 Data Sheet, Rev. 8 Operation. Freescale Semiconductor ...
Page 139
... This bit will be automatically cleared when the wakeup symbol is complete Send wakeup symbol on LIN bus 0 = Normal operation TXABRT — Transmit Abort Message 1 = Transmitter aborts current transmission at next byte boundary; TXABRT resets to 0 after the transmission is successfully aborted 0 = Normal operation Freescale Semiconductor INITREQ ...
Page 140
... UART byte transfer mode enabled 0 = UART byte transfer mode disabled SLCE — SLIC Module Enable 1 = SLIC module enabled 0 = SLIC module disabled 140 SLCWCM 14.9.15 Byte Transfer Mode Operation MC68HC908QL4 Data Sheet, Rev Bit 0 0 BTM SLCE for more detailed Freescale Semiconductor ...
Page 141
... SLIC to proceed and enter SLIC run mode (if SLCE is set). The module will clear INITACK after the module has left reset mode and the SLIC will seek the next LIN header. This bit is read-only SLIC module is in reset state 0 = Normal operation Freescale Semiconductor NOTE 6 5 ...
Page 142
... Maximum Filter Delay (in μs) Digital RX Filter Clock Prescaler SLIC Clock (in MHz) (Divide by (default MC68HC908QL4 Data Sheet, Rev Bit 6 2. 10. 14.9.17 Digital Receive Freescale Semiconductor Filter. ...
Page 143
... The SLIC bit time will not be updated until a write of the SLCBTL has occurred. Bit 7 Read: 0 Write: Reset Unimplemented Figure 14-8. SLIC Bit Time Register High (SLCBTH) Bit 7 Read: BT7 Write: Reset Unimplemented Figure 14-9. SLIC Bit Time Register Low (SLCBTL) Freescale Semiconductor NOTE NOTE BT12 BT11 ...
Page 144
... Byte Transfer Mode NOTE Interrupt Source Interrupts Pending No-Bus-Activity TX Message Buffer Empty Checksum Transmitted Message Buffer Empty RX Message Buffer Full Checksum OK RX Data Buffer Full Errors Bit-Error MC68HC908QL4 Data Sheet, Rev. 8 14.9.16 Operation Bit Priority 0 (Lowest Freescale Semiconductor ...
Page 145
... A unit that is sending a bit on the bus also monitors the bus. A BIT_ERROR must be detected at that bit time, when the bit value that is monitored is different from the bit value that is sent. The SLIC will terminate the data transmission upon detection of a bit error, according to the LIN Freescale Semiconductor I2 I1 ...
Page 146
... An Inconsistent-Synch-Field-Error must be detected if a slave detects the edges of the SYNCH FIELD outside the given tolerance. • Wakeup The wakeup interrupt source indicates that the SLIC module has entered SLIC run mode from SLIC stop mode. 146 NOTE 14.9.7 Handling LIN Message Headers MC68HC908QL4 Data Sheet, Rev. 8 for more Freescale Semiconductor ...
Page 147
... This error comes from the standard UART definition for byte encoding and occurs when STOP is sampled and reads back STOP should always read as 1. • Wakeup The wakeup interrupt source indicates that the SLIC module has entered SLIC run mode from SLIC wait mode. Freescale Semiconductor Table 14-3 shows those interrupt sources which are ...
Page 148
... LIN messaging. Values $08–$3F are for “extended” LIN messaging. DLC[5:0] 148 DLC5 DLC4 DLC3 Table 14-4. Data Length Control Message Data Length (Number of Bytes) $00 1 $01 2 $02 3 ... ... $3D 62 $3E 63 $3F 64 MC68HC908QL4 Data Sheet, Rev Bit 0 DLC2 DLC1 DLC0 14.8.6.1 LIN Freescale Semiconductor ...
Page 149
... TXGO in SLCDLC is set to initiate the transmission. When receiving bytes, they are read from this register only. Bit 7 Read: R7 Write: T7 Reset: 0 Figure 14-13. SLIC Data Register x (SLCD7–SLCD0) R — Read SLC Receive Data T — Write SLC Transmit Data Freescale Semiconductor NOTE . ...
Page 150
... LIN frames and greater than eight bytes for extended LIN frames. The SLIC module will 150 DATA DATA DATA DATA FIELD FIELD FIELD 14.9.7.1 LIN Message MC68HC908QL4 Data Sheet, Rev. 8 Figure 14-14 DATA DATA DATA DATA FIELD FIELD FIELD FIELD Headers. Freescale Semiconductor (shown CHECKSUM FIELD ...
Page 151
... LIN bus, no programming of bit rate is required. At initialization time, the user must configure: • SLIC prescale register (SLIC digital receive filter adjustment). • Wait clock mode operation. Freescale Semiconductor 14.9.13 LIN Data Integrity Checking 14.8.6 SLIC State Vector MC68HC908QL4 Data Sheet, Rev. 8 Initialization/Application Information Methods. Register. ...
Page 152
... SLCWCM — Wait clock mode (default = leaving SLIC clock running when in CPU wait). 3. Write SLCICP to set up prescalers for: a. RXFP — Digital receive filter clock prescaler (default = SLIC divided by 3). 152 14.9.15 Byte Transfer Mode MC68HC908QL4 Data Sheet, Rev. 8 Operation, including Freescale Semiconductor ...
Page 153
... READ SLCSV CLEAR SLCF ERROR CODE ? N READ ID FROM SLCID ID FOR THIS NODE ? Y PROCESS VALID ID Figure 14-15. Handling LIN Message Headers Freescale Semiconductor N INTERRUPT READ SLCSV PROCESS ERROR CODE: BYTE FRAMING ERROR PROCESS ERROR CODE: Y IDENTIFIER-PARITY ERROR BYTE FRAMING ERROR N SET IMSG BIT MC68HC908QL4 Data Sheet, Rev ...
Page 154
... This will delete any previous data which might have been present in the buffer, even though no interrupt is triggered to indicate the arrival of this data. 154 NOTE MC68HC908QL4 Data Sheet, Rev. 8 and 14.9.9 Handling Request LIN Freescale Semiconductor ...
Page 155
... SLCDLC. The two most significant bits of this register are used for special control bits describing the nature of this message frame. Freescale Semiconductor SLIC. deals with command messages, where the SLIC will be receiving MC68HC908QL4 Data Sheet, Rev ...
Page 156
... DECREMENT SW BYTE COUNT BY 8 ERROR CODE ? N N (SW BYTE COUNT £8) MC68HC908QL4 Data Sheet, Rev. 8 EXIT ISR INTERRUPT READ SLCSV CLEAR SLCF PROCESS ERROR CODE: BYTE FRAMING ERROR NO-BUS-ACTIVITY Y ERROR CODE RECEIVE BUFFER OVERRUN ? N EXIT ISR RETURN TO IDLE LAST FRAME ? Y Freescale Semiconductor ...
Page 157
... If the data is successfully received, the user must then empty the buffer by reading SLCD7-SLCD0 and then subtract 8 from the software byte count. When this software counter reaches 8 or fewer, the remaining Freescale Semiconductor NOTE MC68HC908QL4 Data Sheet, Rev. 8 ...
Page 158
... SLCD0, then SLCD1 for the second byte, etc. After all of the bytes to be transmitted are loaded in this way, a single write to SLCDLC will allow the user to encode the number of data bytes to be transmitted (1–8 bytes for standard request frames), set the proper checksum calculation method for the data 158 NOTE MC68HC908QL4 Data Sheet, Rev. 8 Freescale Semiconductor ...
Page 159
... CHECKSUM-ERROR EXIT ISR RETURN TO IDLE TRANSMIT COMPLETE Note 1. When writing TXGO bit only, ensure that CHKMOD and data length values are not accidentally modified. Figure 14-17. Handling Request LIN Message Frames Freescale Semiconductor PROCESS Y 1. CLEAR SLCF 2. INITIALIZE SW BYTE COUNT ? 3. LOAD FIRST 8 DATA BYTES 4 ...
Page 160
... SLIC module. The application software must track the number of sent or received bytes to know what the current 160 NOTE MC68HC908QL4 Data Sheet, Rev. 8 for more detailed explanation Freescale Semiconductor ...
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... Operation. When network activity occurs, the SLIC module will wake the MCU out of stop or wait mode, and return the SLIC module to SLIC run mode. If the SLIC was in SLIC wait mode, normal SLIC interrupt processing Freescale Semiconductor NOTE MC68HC908QL4 Data Sheet, Rev. 8 ...
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... CHKMOD in SLCDLC, as desired, when the identifier for the message frame is decoded. The appropriate calculation for each message frame should be decided at system design time and documented in the LIN description file, indicating to the user which calculation to use for a particular identifier. 162 MC68HC908QL4 Data Sheet, Rev. 8 Freescale Semiconductor ...
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... Refer to Table 14-6 for a more complete list of the digital receive filter delays as they relate to the maximum LIN bus frequency. Table 14-7 Freescale Semiconductor Table 14-5 shows the maximum LIN bit rates Maximum LIN Bit Rate for ±1% SLIC Accuracy for ±1.5% SLIC Accuracy ...
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... Min Pulse Max. Min Pulse Width Bit Rate Allowed (Bits / Allowed (μs) Sec) 4.0 500,000 5.0 400,000 6.7 300,000 8.0 250,000 10.0 200,000 13.3 150,000 16.0 125,000 Freescale Semiconductor shows (1) (1) (1) (1) (1) (1) (1) Width (μs) 2.0 2.5 3.3 4.0 5.0 6.7 8.0 ...
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... CGMXCLK Periods 17.36111 ms Therefore, the closest SLCBT value would be 21 SLIC clocks (SLCBT = 0x0015). Because you can only use even values in SLCBT, the closest acceptable value is 22 (0x0016). Figure 14-18. SLCBT Value Calculation Example 1 Freescale Semiconductor 14-18, Figure 14-19, Figure ...
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... X 1 Bit 500 ns MC68HC908QL4 Data Sheet, Rev. 8 17.36111 Bit 406. SLIC Clock Period 42.67 SLIC Clock Periods = 1 Bit Bit 500 SLIC Clock Period 128 SLIC Clock Periods = 1 Bit 104.004 Bit 500 SLIC Clock Period 208.008 SLIC Clock Periods = 1 Bit Freescale Semiconductor ...
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... The proper closest SLCBT setting would be 34 (0x22), which gives the ideal sample point of 17 SLIC clocks and transmitted bits are 34 SLIC clocks long. Figure 14-22. BTM Mode Receive Byte Sampling Example Freescale Semiconductor FILTER REACHES 0X0 AND TOGGLES FILTER OUTPUT 15 SLIC CLOCKS ...
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... MC68HC908QL4 Data Sheet, Rev. 8 Table 14-7 14-8, and ensure that a single bit time Maximum BTM Bit Rate with Digital RX Filter Set to ÷1 (Bits / Second) (1) (1) 120,000 (1) 120,000 (1) 75,000 120,000 (1) 62,500 120,000 50,000 100,000 37,500 75,000 31,250 62,500 Freescale Semiconductor ...
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... This can be a tremendous advantage to the customer, enabling migration to very low-cost ROM devices which have no non-volatile memory in which to store the trim value. Freescale Semiconductor description for more detail). This means that in some cases MC68HC908QL4 Data Sheet, Rev. 8 ...
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... SLCRX signal stable logic level 0 and the data latch is reset, causing the filtered Rx data 170 NOTE DIGITAL RX FILTER PRESCALER (RXFP[1:0]) 4-BIT UP/DOWN COUNTER 4 EDGE & OUT COUNT COMPARATOR MC68HC908QL4 Data Sheet, Rev. 8 Figure 14-23. FILTERED DATA OUT SLIC CLOCK Freescale Semiconductor ...
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... Freescale Semiconductor Figure 14-23 shows the configuration of the digital receive filter ) is 3 ...
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... Slave LIN Interface Controller (SLIC) Module 172 MC68HC908QL4 Data Sheet, Rev. 8 Freescale Semiconductor ...
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... The TIM clock source is one of the seven prescaler outputs or the external clock input pin, TCLK if available. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register (TSC) select the clock source. Freescale Semiconductor Figure 15-1 MC68HC908QL4 Data Sheet, Rev. 8 ...
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... INTERNAL OSC INTERNAL CLOCK SOURCE 4, 8, 12.8, or 25.6 MHz KEYBOARD INTERRUPT MODULE EXTERNAL INTERRUPT MODULE AUTO WAKEUP MODULE LOW-VOLTAGE INHIBIT 2-CHANNEL 16-BIT TIMER MODULE COP MODULE 6-CHANNEL 10-BIT ADC SLAVE LIN INTERFACE CONTROLLER DEVELOPMENT SUPPORT MONITOR ROM BREAK MODULE Freescale Semiconductor ...
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... When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value. Freescale Semiconductor PRESCALER SELECT PS2 PS1 ...
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... TIM to set the pin if the polarity of the PWM pulse is 0 (ELSxA = 1). OVERFLOW POLARITY = 1 (ELSxA = 0) TCHx POLARITY = 0 TCHx (ELSxA = 1) Figure 15-3. PWM Period and Pulse Width 176 NOTE OVERFLOW PERIOD PULSE WIDTH OUTPUT OUTPUT COMPARE COMPARE MC68HC908QL4 Data Sheet, Rev. 8 OVERFLOW OUTPUT COMPARE Freescale Semiconductor ...
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... TSC0 controls and monitors the buffered PWM function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. Freescale Semiconductor 15.8.1 TIM Status and Control NOTE MC68HC908QL4 Data Sheet, Rev ...
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... The result duty cycle output. Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty cycle output. See 15.8.1 TIM Status and Control 178 NOTE NOTE Register. MC68HC908QL4 Data Sheet, Rev. 8 Table 15-2. Table 15-2. Freescale Semiconductor ...
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... BCFE is cleared. After the break, doing the second step clears the status bit. 15.7 I/O Signals The TIM module can share its pins with the general-purpose I/O pins. See that are shared. Freescale Semiconductor MC68HC908QL4 Data Sheet, Rev. 8 Interrupts sheet. Figure 15-1 ...
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... If another TIM overflow occurs before the clearing sequence is complete, then writing 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Writing TOF has no effect Counter has reached modulo value 0 = Counter has not reached modulo value 180 TOIE TSTOP TRST MC68HC908QL4 Data Sheet, Rev Bit 0 PS2 PS1 PS0 Freescale Semiconductor ...
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... Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers. Freescale Semiconductor NOTE NOTE Table 15-1 ...
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... NOTE Bit 14 Bit 13 Bit 12 Bit Bit 6 Bit 5 Bit 4 Bit Bit14 Bit13 Bit12 Bit11 Bit6 Bit5 Bit4 Bit3 NOTE MC68HC908QL4 Data Sheet, Rev Bit 0 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Bit 0 Bit10 Bit9 Bit8 Bit 0 Bit2 Bit1 Bit0 Freescale Semiconductor ...
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... MSxB — Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TSC0. Setting MS0B causes the contents of TSC1 to be ignored by the TIM and reverts TCH1 to general-purpose I/ Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled Freescale Semiconductor MS0B ...
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... Output compare or PWM 0 Clear output on compare 1 Set output on compare 1 Toggle output on compare Buffered output 0 compare or Clear output on compare buffered PWM 1 Set output on compare Table 15-2 shows how ELSxB and ELSxA work. NOTE NOTE MC68HC908QL4 Data Sheet, Rev. 8 Table 15-2). Configuration Freescale Semiconductor ...
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... Reset: Figure 15-12. TIM Channel x Register High (TCHxH) Bit 7 Read: Bit 7 Write: Reset: Figure 15-13. TIM Channel Register Low (TCHxL) Freescale Semiconductor shows, the CHxMAX bit takes effect in the cycle after it is set OVERFLOW OVERFLOW OUTPUT OUTPUT COMPARE COMPARE Figure 15-11. CHxMAX Latency ...
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... Timer Interface Module (TIM) 186 MC68HC908QL4 Data Sheet, Rev. 8 Freescale Semiconductor ...
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... When a CPU generated address matches the contents of the break address registers, the break interrupt is generated. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the microcontroller unit (MCU) to normal operation. Figure 16-2 shows the structure of the break module. Freescale Semiconductor MC68HC908QL4 Data Sheet, Rev. 8 187 ...
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... INTERNAL OSC INTERNAL CLOCK SOURCE 4, 8, 12.8, or 25.6 MHz KEYBOARD INTERRUPT MODULE EXTERNAL INTERRUPT MODULE AUTO WAKEUP MODULE LOW-VOLTAGE INHIBIT 2-CHANNEL 16-BIT TIMER MODULE COP MODULE 6-CHANNEL 10-BIT ADC SLAVE LIN INTERFACE CONTROLLER DEVELOPMENT SUPPORT MONITOR ROM BREAK MODULE Freescale Semiconductor ...
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... A break interrupt stops the timer counter and inhibits input captures. 16.2.1.3 COP During Break Interrupts The COP is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary register (BRKAR). Freescale Semiconductor ADDRESS BUS[15:8] BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR ...
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... Figure 16-4. Break Address Register High (BRKH) Bit 7 Read: Bit 7 Write: Reset: 0 Figure 16-5. Break Address Register Low (BRKL) 190 Bit 14 Bit 13 Bit 12 Bit Bit 6 Bit 5 Bit 4 Bit MC68HC908QL4 Data Sheet, Rev Bit Bit 0 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Freescale Semiconductor ...
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... This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break Freescale Semiconductor ...
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... No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. 192 ( reset vector is blank ($FFFE and $FFFF contain TST is applied to IRQ TST MC68HC908QL4 Data Sheet, Rev. 8 Figure 16-10, Figure 16-11, on IRQ. The IRQ pin must TST Freescale Semiconductor ...
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... FROM Table 16-1 RESET VECTOR BLANK? YES FORCED MONITOR MODE DEBUGGING AND FLASH PROGRAMMING (IF FLASH IS ENABLED) Figure 16-9. Simplified Monitor Mode Entry Flowchart Freescale Semiconductor POR RESET YES NO IRQ = V ? TST NO PTA1 = 1, AND NORMAL USER MODE MONITOR MODE HOST SENDS 8 SECURITY BYTES ...
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... MC68HC908QL4 Data Sheet, Rev RST (PTA3) OSC1 (PTA5) PTA1 IRQ (PTA2) PTA4 PTA0 Value not critical N.C. RST (PTA3 OSC1 (PTA5) PTA1 * IRQ (PTA2) PTA4 PTA0 V SS Freescale Semiconductor V DD 0.1 μ kΩ kΩ 0.1 μF N.C. N.C. ...
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... PTA1 and PTA4 pins can be changed. Once out of reset, the MCU waits for the host to send eight security bytes (see security bytes, the MCU sends a break signal (10 consecutive 0s) to the host, indicating that it is ready to receive a command. Freescale Semiconductor μF 1 μ ...
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... Rate 9.8304 2.4576 Provide external 9600 MHz MHz clock at OSC1. 9.8304 2.4576 Provide external 9600 MHz MHz clock at OSC1. 3.2 MHz Internal clock is X 9600 (Trimmed) active OSC1 — — [13] TST lowered, the BIH and TST is applied to IRQ TST Freescale Semiconductor is . ...
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... Modes Reset Vector High Vector Low User $FFFE Monitor $FEFE Freescale Semiconductor NOTE , the MCU will come out of reset in user mode. Internal TST Figure 16-12. NOTE Table 16-2. Mode Differences Functions ...
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... Wait one bit time after each echo before sending the next byte. 198 BIT 6 BIT 2 BIT 3 BIT 4 BIT 5 Figure 16-13. Monitor Data Format MISSING STOP BIT APPROXIMATELY 2 BITS DELAY BEFORE ZERO ECHO Figure 16-14. Break Transaction Table 16-1. NOTE MC68HC908QL4 Data Sheet, Rev. 8 NEXT START STOP BIT 7 BIT BIT Freescale Semiconductor ...
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... Table 16-3. READ (Read Memory) Command Description Read byte from memory Operand 2-byte address in high-byte:low-byte order Data Returned Returns contents of specified address Opcode $4A SENT TO MONITOR READ READ ECHO Freescale Semiconductor ADDRESS ADDRESS ADDRESS ADDRESS HIGH HIGH LOW LOW Figure 16-15. Read Transaction ...
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... A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64-Kbyte memory map. 200 Command Sequence ADDRESS ADDRESS ADDRESS ADDRESS HIGH HIGH LOW LOW Command Sequence FROM HOST IREAD IREAD DATA Command Sequence FROM HOST DATA DATA IWRITE IWRITE ECHO MC68HC908QL4 Data Sheet, Rev. 8 DATA DATA DATA RETURN Freescale Semiconductor ...