MC908QL4MDT Freescale Semiconductor, MC908QL4MDT Datasheet - Page 161

• Manufacturer Part Number: MC908QL4MDT
• Description: IC MCU 8BIT 4K FLASH 16-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908QL4MDT

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LIN (Local Interconnect Network)
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

14.9.9.3 Transmit Abort
The transmit abort bit (TXABRT) in SLCC1 allows the user to cease transmission of data on the next byte
boundary. When this bit is set to 1, it will finish transmitting the byte currently being transmitted, then
cease transmission. After the transmission is successfully aborted, TXABRT will automatically be reset
by the SLIC to 0. If the SLIC is not in process of transmitting at the time TXABRT is written to 1, there is
no effect and TXABRT will read back as 0.
14.9.9.4 Possible Errors on Request Message Data
Possible errors on request message data are:
14.9.10 Handling IMSG to Minimize Interrupts
The IMSG feature is designed to minimize the number of interrupts required to maintain LIN
communications. On a network with many slave nodes, it is very likely that a particular slave will observe
messages which are not intended for that node. When the SLIC module detects any message header, it
synchronizes to that message frame and bit rate, then interrupts the CPU after the identifier byte has been
successfully received and parity checked. At this time, if the software determines that the message may
be ignored, IMSG may be set to indicate to the module that the data field of the message frame is to be
ignored and no additional interrupts should be generated until the next valid message header is received.
The bit is automatically reset to 0 after the current message frame is complete and the LIN bus returns to
idle state. This reduces the load on the CPU and allows the application software to immediately begin
performing any operations which might otherwise not be allowed while receiving messaging.
14.9.11 Sleep and Wakeup Operation
The SLIC module itself has no special sleep mode, but does support low-power modes and wake-up on
network activity. For low-power operations, the user must select whether or not to allow the SLIC clock to
continue operating when the MCU issues a wait instruction through the SLC wait clock mode (SLCWCM)
bit in SLCC1. If SLCWCM = 1, the SLIC will enter SLIC STOP mode when the MCU executes a WAIT
instruction. If SLCWCM = 0, the SLIC will enter SLIC WAIT mode when the MCU executes a WAIT
instruction. For more information on these modes, as well as wakeup options from these modes, please
refer to
When network activity occurs, the SLIC module will wake the MCU out of stop or wait mode, and return
the SLIC module to SLIC run mode. If the SLIC was in SLIC wait mode, normal SLIC interrupt processing
Freescale Semiconductor
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Byte Framing Error
Checksum-Error (LIN specified error)
Bit-Error
14.5 Modes of
byte count in the SLIC is. If programming in C, make sure to use the
STATIC modifier on this variable (or make it a global variable) to ensure
that it keeps its value between interrupts.
IMSG will prevent another interrupt from occurring for the current message
frame, however if data bytes are appearing on the bus they may be
received and copied into the message buffer. This will delete any previous
data which might have been present in the buffer, even though no interrupt
is triggered to indicate the arrival of this data.
Operation.
MC68HC908QL4 Data Sheet, Rev. 8
NOTE
Initialization/Application Information
161