HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 116

• Manufacturer Part Number: HD6417020SVX12I
• Description: IC SUPERH MPU ROMLESS 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SVX12I

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 12.5MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Table 8.2
Name
Bus control register
Wait state control register 1
Wait state control register 2
Wait state control register 3
DRAM area control register
Parity control register
Refresh control register
Refresh timer control/status register
Refresh timer counter
Refresh time constant register
Notes: 1. Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
8.1.5
The SH microprocessors have 32-bit address spaces on the architecture, but the top 4 bits are
ignored. Table 8.3 outlines the division of space. As shown, the space is divided into areas 0–7 by
the value of the top addresses.
Each area is allocated a specific type of space. When the area is accessed, a strobe signal that
matches the type of area space is generated. This allocates peripheral LSIs and memory devices
according to the type of the area spaces and allows them to be directly linked to this LSI. Some
areas are of a fixed type based on their address while others can be selected in registers.
Area 0 can be used as an on-chip ROM space or external memory space. Area 1 can be used as
DRAM space or external memory space. DRAM space enables direct connection to DRAM and
outputs RAS, CAS and multiplexed addresses. Areas 2–4 can only be used as external memory
space. Area 5 can be used as on-chip peripheral module space or external memory space. Area 6
can be used as address/data multiplexed I/O space or external memory space. For address/data
multiplexed I/O space, an address and data are multiplexed and input/output from AD15–AD0
pins. Area 7 can be used as on-chip RAM space or external memory space.
The bus width of the data bus is basically switched between 8 bit and 16 bit by the value of
address bit A27. For the following areas, however, the bus width is determined by conditions other
than the A27 bit value.
96 RENESAS
2. Write only with word transfer instructions. See section 8.2.11, Register Access, for
Overview of Areas
details on the register addresses, see section 8.3.5, Description of Areas.
details on writing.
Register Configuration
Abbr.
BCR
WCR1
WCR2
WCR3
DCR
PCR
RCR
RTCSR
RTCNT
RTCOR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
H'0000
H'FFFF
H'FFFF
H'F800
H'0000
H'0000
H'0000
H'0000
H'0000
H'00FF
Address*
H'5FFFFA0
H'5FFFFA2
H'5FFFFA4
H'5FFFFA6
H'5FFFFA8
H'5FFFFAA 8,16,32
H'5FFFFAC 8,16,32*
H'5FFFFAE 8,16,32*
H'5FFFFB0
H'5FFFFB2
1
Bus width
8,16,32
8,16,32
8,16,32
8,16,32
8,16,32
8,16,32*
8,16,32*
2
2
2
2