HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 392

• Manufacturer Part Number: HD6417020SVX12I
• Description: IC SUPERH MPU ROMLESS 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SVX12I

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 12.5MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

In receiving, the SCI operates as follows:
1. The SCI monitors the receive data line. When it detects a start bit (0), the SCI synchronizes
2. Receive data is shifted into the RSR in order from the LSB to the MSB.
3. The parity bit and stop bit are received. After receiving these bits, the SCI makes the following
4. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in the
Figure 13.8 shows an example of SCI receive operation in the asynchronous mode.
Table 13.11 Receive Error Conditions and SCI Operation
Receive Error
Overrun error
Framing error
Parity error
internally and starts receiving.
checks:
a. Parity check: The number of 1s in the receive data must match the even or odd parity
b. Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first stop bit
c. Status check: RDRF must be 0 so that receive data can be loaded from the RSR into the
If these checks all pass, the SCI sets RDRF to 1 and stores the received data in the RDR. If one
of the checks fails (receive error), the SCI operates as indicated in table 13.11.
Note:
SCR, the SCI requests a receive-data-full interrupt (RXI). If one of the error flags (ORER,
PER, or FER) is set to 1 and the receive-data-full interrupt enable bit (RIE) in the SCR is also
set to 1, the SCI requests a receive-error interrupt (ERI).
setting of the O/E bit in the SMR.
is checked.
RDR.
When a receive error flag is set, further receiving is disabled. The RDRF bit is not set
to 1. Be sure to clear the error flags.
Abbreviation
ORER
FER
PER
Condition
Receiving of next data ends while
RDRF is still set to 1 in SSR
Stop bit is 0
Parity of receive data differs from
even/odd parity setting in SMR
Data Transfer
Receive data not loaded
from RSR into RDR
Receive data loaded from
RSR into RDR
Receive data loaded from
RSR into RDR
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