HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 20

• Manufacturer Part Number: HD6417020SVX12I
• Description: IC SUPERH MPU ROMLESS 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SVX12I

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 12.5MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13.2 Register Descriptions......................................................................................................... 344
13.3 Operation ........................................................................................................................... 363
13.4 SCI Interrupt Sources and the DMAC............................................................................... 394
13.5 Usage Notes ....................................................................................................................... 394
Section 14 Pin Function Controller (PFC)
14.1 Overview............................................................................................................................ 399
14.2 Register Configuration ...................................................................................................... 401
14.3 Register Descriptions......................................................................................................... 401
Section 15 Parallel I/O Ports
15.1 Overview............................................................................................................................ 415
15.2 Port A................................................................................................................................. 415
15.3 Port B ................................................................................................................................. 417
Section 16 ROM
16.1 Overview............................................................................................................................ 419
16.2 PROM Mode...................................................................................................................... 421
13.1.2 Block Diagram...................................................................................................... 342
13.1.3 Input/Output Pins.................................................................................................. 343
13.1.4 Register Configuration ......................................................................................... 343
13.2.1 Receive Shift Register .......................................................................................... 344
13.2.2 Receive Data Register .......................................................................................... 344
13.2.3 Transmit Shift Register ........................................................................................ 344
13.2.4 Transmit Data Register......................................................................................... 345
13.2.5 Serial Mode Register ............................................................................................ 345
13.2.6 Serial Control Register ......................................................................................... 347
13.2.7 Serial Status Register............................................................................................ 351
13.2.8 Bit Rate Register (BRR)....................................................................................... 355
13.3.1 Overview .............................................................................................................. 363
13.3.2 Operation in Asynchronous Mode........................................................................ 366
13.3.3 Multiprocessor Communication ........................................................................... 376
13.3.4 Clocked Synchronous Operation.......................................................................... 384
14.3.1 Port A I/O Register (PAIOR) ............................................................................... 401
14.3.2 Port A Control Registers (PACR1 and PACR2) .................................................. 402
14.3.3 Port B I/O Register (PBIOR)................................................................................ 407
14.3.4 Port B Control Registers (PBCR1 and PBCR2)................................................... 408
14.3.5 Column Address Strobe Pin Control Register (CASCR) ..................................... 413
15.2.1 Register Configuration ......................................................................................... 415
15.2.2 Port A Data Register (PADR) .............................................................................. 416
15.3.1 Register Configuration ......................................................................................... 417
15.3.2 Port B Data Register (PBDR)............................................................................... 418
16.2.1 Setting the PROM Mode ...................................................................................... 421
.................................................................................................................. 419
............................................................................................ 415
................................................................... 399