HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 122

• Manufacturer Part Number: HD6417020SVX12I
• Description: IC SUPERH MPU ROMLESS 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SVX12I

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 12.5MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Table 8.4
Bits 15–8:
DRW7–DRW0
0
1
Note: Sampled in the address/data multiplexed I/O space.
• Bits 7–0 (single-mode DMA memory write wait state control (DWW7–DWW0)): DWW7–
102 RENESAS
DWW0 determine the number of states in single-mode DMA memory write cycles for each
area and whether or not to sample the WAIT signal. Bits DWW7–DWW0 correspond to areas
7–0, respectively. If a bit is cleared to 0, the WAIT signal is not sampled during the single-
mode DMA memory write cycle for the corresponding area. If it is set to 1, sampling takes
place.
The number of states for areas accesses based on bit settings are the same as indicated for
single-mode DMA memory read cycles. See bits 15–8, wait state control during single-mode
DMA memory transfer (DRW7–DRW0), for details.
Table 8.5 summarizes single-mode DMA memory write cycle state information.
Single-Mode DMA Memory Read Cycle States (External Memory Space)
Description
WAIT Pin Input
Signal
Not sampled during
single-mode DMA
memory read cycle*
Sampled during
single-mode DMA
memory read cycle
(initial value)
External Memory
Space
Areas 1, 3–5,7: 1 state,
fixed
Areas 0, 2, 6: 1 state +
long wait state
Areas 1, 3–5, 7: 2 states
+ wait states from WAIT
Areas 0, 2, 6: 1 state +
long wait state + Wait
state from WAIT
Single-Mode DMA Memory Read Cycle States
(External Memory Space)
DRAM Space
Column address
cycle: 1 state,
fixed (short
pitch)
Column address
cycle: 2 states +
wait state from
WAIT (long
pitch)
Multiplexed
I/O
4 states +
wait states
from WAIT