HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 17

• Manufacturer Part Number: HD6417020SVX12I
• Description: IC SUPERH MPU ROMLESS 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SVX12I

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 12.5MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

9.1
9.2
9.3
9.4
9.5
Section 10 16-Bit Integrated-Timer Pulse Unit (ITU)
10.1 Overview............................................................................................................................ 213
10.2 ITU Register Descriptions ................................................................................................. 224
Overview............................................................................................................................ 169
9.1.1
9.1.2
9.1.3
9.1.4
Register Descriptions......................................................................................................... 174
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
Operation ........................................................................................................................... 182
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
Examples of Use................................................................................................................ 206
9.4.1
9.4.2
Cautions ............................................................................................................................. 208
10.1.1 Features ................................................................................................................ 213
10.1.2 Block Diagram...................................................................................................... 216
10.1.3 Input/Output Pins.................................................................................................. 221
10.1.4 Register Configuration ......................................................................................... 222
10.2.1 Timer Start Register (TSTR)................................................................................ 224
10.2.2 Timer Synchro Register (TSNC).......................................................................... 226
10.2.3 Timer Mode Register (TMDR) ............................................................................ 227
10.2.4 Timer Function Control Register (TFCR)............................................................ 230
10.2.5 Timer Output Control Register (TOCR) .............................................................. 231
10.2.6 Timer Counters (TCNT)....................................................................................... 232
10.2.7 General Registers A and B (GRA and GRB) ....................................................... 233
10.2.8 Buffer Registers A and B (BRA, BRB)................................................................ 234
10.2.9 Timer Control Register (TCR) ............................................................................. 235
10.2.10 Timer I/O Control Register (TIOR) ..................................................................... 237
10.2.11 Timer Status Register (TSR) ................................................................................ 239
10.2.12 Timer Interrupt Enable Register (TIER) .............................................................. 240
Features ................................................................................................................ 169
Block Diagram...................................................................................................... 170
Pin Configuration ................................................................................................. 172
Register Configuration ......................................................................................... 173
DMA Source Address Registers 0–3 (SAR0–SAR3) .......................................... 174
DMA Destination Address Registers 0-3 (DAR0–DAR3) .................................. 174
DMA Transfer Count Registers 0–3 (TCR0–TCR3) ........................................... 175
DMA Channel Control Registers 0–3 (CHCR0–CHCR3)................................... 175
DMA Operation Register (DMAOR)................................................................... 180
DMA Transfer Flow ............................................................................................. 182
DMA Transfer Requests....................................................................................... 184
Channel Priority.................................................................................................... 186
DMA Transfer Types ........................................................................................... 191
Number of Bus Cycle States and DREQ Pin Sample Timing.............................. 198
DMA Transfer Ending Conditions ....................................................................... 205
DMA Transfer between On-Chip RAM and a Memory-Mapped
External Device .................................................................................................... 206
Example of DMA Transfer between On-Chip SCI and External Memory.......... 207
............................................ 213