HD64F3048BF25 Renesas Electronics America, HD64F3048BF25 Datasheet - Page 183

• Manufacturer Part Number: HD64F3048BF25
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048BF25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Figure 6.19 shows the timing when the bus right is requested by an external bus master during a
read cycle in a two-state-access area. There is a minimum interval of two states from when the
BREQ signal goes low until the bus is released.
Figure 6.19 External-Bus-Released State (Two-State-Access Area, During Read Cycle)
Address
bus
CS
Data bus
AS
HWR
BREQ
BACK
1
2
3
4, 5
6
Note: n = 7 to 0
n
,
RD
Low
BACK
BREQ
High
BACK
,
LWR
BREQ
BREQ
signal goes low at end of CPU read cycle, releasing bus right to external bus master.
signal goes high, ending bus-release cycle.
pin continues to be sampled while bus is released to external bus master.
High
signal is sampled twice consecutively.
signal is sampled at rise of T state.
1
CPU cycles
Minimum 2 cycles
T
Address
1
T
1
2
2
3
External bus released
Rev. 3.00 Sep 27, 2006 page 155 of 872
High-impedance
High-impedance
High-impedance
High-impedance
High level
4
Section 6 Bus Controller
5
REJ09B0325-0300
6
CPU cycles