HD64F3048BF25 Renesas Electronics America, HD64F3048BF25 Datasheet - Page 92

• Manufacturer Part Number: HD64F3048BF25
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048BF25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 2 CPU
2.8.4
Reset Exception Handling: Reset exception handling has the highest priority. The reset state is
entered when the RES signal goes low. Reset exception handling starts after that, when RES
changes from low to high. When reset exception handling starts the CPU fetches a start address
from the exception vector table and starts program execution from that address. All interrupts,
including NMI, are disabled during the reset exception-handling sequence and immediately after it
ends.
Interrupt Exception Handling and Trap Instruction Exception Handling: When these
exception-handling sequences begin, the CPU references the stack pointer (ER7) and pushes the
program counter and condition code register on the stack. Next, if the UE bit in the system control
register (SYSCR) is set to 1, the CPU sets the I bit in the condition code register to 1. If the UE bit
Rev. 3.00 Sep 27, 2006 page 64 of 872
REJ09B0325-0300
Notes: 1.
RES = High
Exception-handling state
Bus-released state
2.
Exception-Handling Sequences
Reset state *
From any state except hardware standby mode, a transition to the reset state occurs
whenever RES goes low.
From any state, a transition to hardware standby mode occurs when STBY goes low.
End of
exception
handling
End of bus
release
1
Bus
request
STBY = High, RES = Low
Figure 2.13 State Transitions
Program execution state
NMI, IRQ , IRQ ,
or IRQ interrupt
Exception
End of bus release
Interrupt
Bus request
2
0
1
SLEEP instruction
with SSBY = 1
SLEEP
instruction
with SSBY = 0
Hardware standby mode *
Software standby mode
Power-down state
Sleep mode
2