HD64F3048BF25 Renesas Electronics America, HD64F3048BF25 Datasheet - Page 564

• Manufacturer Part Number: HD64F3048BF25
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048BF25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 14 Smart Card Interface
Interrupt Operations
The smart card interface has three interrupt sources: transmit-data-empty (TXI), transmit/receive-
error (ERI), and receive-data-full (RXI). The transmit-end interrupt request (TEI) is not available
in smart card mode.
A TXI interrupt is requested when the TEND flag is set to 1 in SSR. An RXI interrupt is requested
when the RDRF flag is set to 1 in SSR. An ERI interrupt is requested when the ORER, PER, or
ERS flag is set to 1 in SSR. These relationships are shown in table 14.8.
Table 14.8 Smart Card Mode Operating States and Interrupt Sources
Operating State
Transmit mode
Receive mode
Data Transfer by DMAC
The DMAC can be used to transmit and receive in smart card mode, as in normal SCI operations.
In transmit mode, when the TEND flag is set to 1 in SSR, the TDRE flag is set simultaneously,
generating a TXI interrupt. If TXI is designated in advance as a DMAC activation source, the
DMAC will be activated by the TXI request and will transfer the next transmit data. This data
transfer by the DMAC automatically clears the TDRE and TEND flags to 0. When an error occurs,
the SCI automatically retransmits the same data, keeping TEND cleared to 0 so that the DMAC is
not activated. The SCI and DMAC will therefore automatically transmit the designated number of
bytes, including retransmission when an error occurs. When an error occurs the ERS flag is not
cleared automatically, so the RIE bit should be set to 1 to enable the error to generate an ERI
request, and the ERI interrupt handler should clear ERS.
When using the DMAC to transmit or receive, first set up and enable the DMAC, then make SCI
settings. DMAC settings are described in section 8, DMA Controller.
In receive operations, when the RDRF flag is set to 1 in SSR, an RXI interrupt is requested. If RXI
is designated in advance as a DMAC activation source, the DMAC will be activated by the RXI
request and will transfer the received data. This data transfer by the DMAC automatically clears
the RDRF flag to 0. When an error occurs, the RDRF flag is not set and an error flag is set instead.
The DMAC is not activated. The ERI interrupt request is directed to the CPU. The ERI interrupt
handler should clear the error flags.
Rev. 3.00 Sep 27, 2006 page 536 of 872
REJ09B0325-0300
Normal operation
Error
Normal operation
Error
RDRF
Flag
TEND
ERS
PER, ORER
Mask Bit
TIE
RIE
RIE
RIE
Interrupt
Source
TXI
ERI
RXI
ERI
DMAC
Activation
Available
Not available
Available
Not available