MC9S08RD32CFGE Freescale Semiconductor, MC9S08RD32CFGE Datasheet - Page 32

• Manufacturer Part Number: MC9S08RD32CFGE
• Description: IC MCU 32K FLASH 8MHZ 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08RD32CFGE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Modes of Operation
into stop2, the states of the I/O pins are latched. The states are held while in stop2 mode and after exiting
stop2 mode until a 1 is written to PPDACK in SPMSC2.
Exit from stop2 is done by asserting any of the wakeup pins: RESET, IRQ, or KBI1 that have been enabled,
or through the real-time interrupt. IRQ and KBI1 pins are always active-low when used as wakeup pins in
stop2 regardless of how they were configured before entering stop2. (KBI2 will not wake the MCU from
stop2.)
Upon wakeup from stop2 mode, the MCU will start up as from a power-on reset (POR) except pin states
remain latched. The CPU will take the reset vector. The system and all peripherals will be in their default
reset states and must be initialized.
After waking up from stop2, the PPDF bit in SPMSC2 is set. This flag may be used to direct user code to
go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until a 1 is written
to PPDACK in SPMSC2.
For pins that were configured as general-purpose I/O, the user must copy the contents of the I/O port
registers, which have been saved in RAM, back to the port registers before writing to the PPDACK bit. If
the port registers are not restored from RAM before writing to PPDACK, then the register bits will be in
their reset states when the I/O pin latches are opened and the I/O pins will switch to their reset states.
For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that
interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before
writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O
latches are opened.
3.6.3
Stop3 Mode
Upon entering stop3 mode, all of the clocks in the MCU, including the oscillator itself, are halted. The
OSC is turned off, the ACMP is disabled, and the voltage regulator is put in standby. The states of all of
the internal registers and logic, as well as the RAM content, are maintained. The I/O pin states are not
latched at the pin as in stop2. Instead they are maintained by virtue of the states of the internal logic driving
the pins being maintained.
Exit from stop3 is done by asserting RESET, any asynchronous interrupt pin that has been enabled, or
through the real-time interrupt. The asynchronous interrupt pins are the IRQ or KBI1 and KBI2 pins.
If stop3 is exited by means of the RESET pin, then the MCU will be reset and operation will resume after
taking the reset vector. Exit by means of an asynchronous interrupt or the real-time interrupt will result in
the MCU taking the appropriate interrupt vector.
A separate self-clocked source (≈1 kHz) for the real-time interrupt allows a wakeup from stop2 or stop3
mode with no external components. When RTIS2:RTIS1:RTIS0 = 0:0:0, the real-time interrupt function
and this 1-kHz source are disabled. Power consumption is lower when the 1-kHz source is disabled, but in
that case the real-time interrupt cannot wake the MCU from stop.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
32
Freescale Semiconductor