MC9S08RD32CFGE Freescale Semiconductor, MC9S08RD32CFGE Datasheet - Page 66

• Manufacturer Part Number: MC9S08RD32CFGE
• Description: IC MCU 32K FLASH 8MHZ 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08RD32CFGE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Resets, Interrupts, and System Configuration
1. The ILAD bit is only present in 16K and 8K versions of the devices.
2. Any of these reset sources that are active at the time of reset will cause the corresponding bit(s) to be set; bits corresponding
66
to sources that are not active at the time of reset will be cleared.
Any other
Field
ILOP
ILAD
POR
COP
LVD
PIN
7
6
5
4
3
1
reset:
POR
LVR
W
R
u = Unaffected by reset
Power-On Reset — Reset was caused by the power-on detection logic. Because the internal supply voltage was
ramping up at the time, the low-voltage reset (LVR) status bit is also set to indicate that the reset occurred while
the internal supply was below the LVR threshold.
0 Reset not caused by POR.
1 POR caused reset.
External Reset Pin — Reset was caused by an active-low level on the external reset pin.
0 Reset not caused by external reset pin.
1 Reset came from external reset pin.
Computer Operating Properly (COP) Watchdog — Reset was caused by the COP watchdog timer timing out.
This reset source may be blocked by COPE = 0.
0 Reset not caused by COP timeout.
1 Reset caused by COP timeout.
Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP
instruction is considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction is
considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register.
0 Reset not caused by an illegal opcode.
1 Reset caused by an illegal opcode.
Illegal Address Access — Reset was caused by an attempt to access a designated illegal address.
0 Reset not caused by an illegal address access
1 Reset caused by an illegal address access
Illegal address areas only exist in the 16K and 8K versions and are defined as:
Unused and reserved locations in register areas are not considered designated illegal addresses and do not
trigger illegal address resets.
Low Voltage Detect — If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset
occurs. This bit is also set by POR.
0 Reset not caused by LVD trip or POR
1 Reset caused by LVD trip or POR
• $0440–$17FF — Gap from end of RAM to start of high-page registers
• $1834–$BFFF — Gap from end of high-page registers to start of FLASH memory
POR
1
u
0
7
PIN
(2)
6
0
0
Writing any value to SRS address clears COP watchdog timer.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Figure 5-3. System Reset Status (SRS)
Table 5-3. SRS Field Descriptions
COP
(2)
0
0
5
ILOP
(2)
4
0
0
Description
ILAD
(2)
0
0
3
(1)
2
0
0
0
0
Freescale Semiconductor
LVD
1
1
0
1
0
0
0
0
0