MCHC908GR8AVFAE Freescale Semiconductor, MCHC908GR8AVFAE Datasheet - Page 158

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MCHC908GR8AVFAE

Manufacturer Part Number
MCHC908GR8AVFAE
Description
IC MCU 8K FLASH 8MHZ 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MCHC908GR8AVFAE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
21
Program Memory Size
7.5KB (7.5K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCHC908GR8AVFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
System Integration Module (SIM)
The SIM is responsible for:
Table 14-1
158
Addr.
$FE00
$FE01
$FE03
$FE04
$FE05
$FE06
Bus clock generation and control for CPU and peripherals:
Master reset control, including power-on reset (POR) and computer operating properly (COP)
timeout
Interrupt arbitration
SIM Break Status Register
SIM Reset Status Register
Stop/wait/reset/break entry and recovery
Internal clock control
SIM Break Flag Control
Signal Name
Register Name
shows the internal signal names used in this section.
CGMXCLK
CGMVCLK
CGMOUT
PORRST
Register (SBFCR)
IRST
R/W
Register 1 (INT1)
Register 2 (INT2)
Register 3 (INT3)
IAB
IDB
Interrupt Status
Interrupt Status
Interrupt Status
See page 171.
See page 172.
See page 173.
See page 167.
See page 168.
See page 168.
(SRSR)
(SBSR)
Buffered version of OSC1 from clock generator module (CGM)
PLL output
PLL-based or OSC1-based clock output from CGM module
(Bus clock = CGMOUT divided by two)
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
POR:
Figure 14-2. SIM I/O Register Summary
Table 14-1. Signal Name Conventions
1. Writing a 0 clears SBSW.
BCFE
Bit 7
POR
IF14
IF6
R
R
R
R
0
1
0
0
0
0
0
= Unimplemented
IF13
PIN
IF5
R
R
R
R
R
6
0
0
0
0
0
0
COP
IF12
IF4
R
R
R
R
R
5
0
0
0
0
0
0
Description
ILOP
IF11
IF3
R
R
R
R
R
R
4
0
0
0
0
0
0
= Reserved
ILAD
IF10
IF2
R
R
R
R
R
3
0
0
0
0
0
0
MODRST
IF1
IF9
R
R
R
R
R
2
0
0
0
0
0
0
Freescale Semiconductor
Note
SBSW
IF16
LVI
IF8
R
R
R
R
1
0
0
0
0
0
0
(1)
Bit 0
IF15
IF7
R
R
R
R
R
0
0
0
0
0
0
0

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