MCHC908GR8AVFAE Freescale Semiconductor, MCHC908GR8AVFAE Datasheet - Page 42

• Manufacturer Part Number: MCHC908GR8AVFAE
• Description: IC MCU 8K FLASH 8MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908GR8AVFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Memory
2.6.6 FLASH Block Protection
Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target
application, provision is made for protecting a block of memory from unintentional erase or program
operations due to system malfunction. This protection is done by using of a FLASH block protect register
(FLBPR). The FLBPR determines the range of the FLASH memory which is to be protected. The range
of the protected area starts from a location defined by FLBPR and ends at the bottom of the FLASH
memory ($FFFF). When the memory is protected, the HVEN bit cannot be set in either ERASE or
PROGRAM operations.
When the FLBPR is program with all 0’s, the entire memory is protected from being programmed and
erased. When all the bits are erased (all 1’s), the entire memory is accessible for program and erase.
When bits within the FLBPR are programmed, they lock a block of memory, address ranges as shown in
2.6.7 FLASH Block Protect
any erase or program of the FLBPR or the protected block of FLASH memory is prohibited. Mass erase
is disabled whenever any block is protected (FLBPR does not equal $FF). The presence of a V
IRQ pin will bypass the block protection so that all of the memory included in the block protect register is
open for program and erase operations.
42
Do not exceed t
cumulative high voltage programming time to the same row before next
erase. t
Refer to
The time between programming the FLASH address change (step 7 to
step 7), or the time between the last FLASH programmed to clearing the
PGM bit (step 7 to step 10) must not exceed the maximum programming
time, t
Be cautious when programming the FLASH array to ensure that
non-FLASH locations are not used as the address that is written to when
selecting either the desired row address range in step 3 of the algorithm or
the byte to be programmed in step 7 of the algorithm. This applies
particularly to $FFD4–$FFDF.
In performing a program or erase operation, the FLASH block protect
register must be read after setting the PGM or ERASE bit and before
asserting the HVEN bit
The FLASH block protect register is not protected with special hardware or
software. Therefore, if this page is not protected by FLBPR the register is
erased by either a page or mass erase operation.
PROG
HV
19.17 Memory
must satisfy this condition:
maximum.
Register. Once the FLBPR is programmed with a value other than $FF or $FE,
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
t
NVS
PROG
+ t
NVH
maximum or t
Characteristics.
+ t
PGS
+ (t
CAUTION
NOTE
NOTE
NOTE
NOTE
PROG
HV
maximum. t
x 32) ≤ t
HV
HV
maximum
is defined as the
Freescale Semiconductor
TST
on the