MCHC908GR8AVFAE Freescale Semiconductor, MCHC908GR8AVFAE Datasheet - Page 208

• Manufacturer Part Number: MCHC908GR8AVFAE
• Description: IC MCU 8K FLASH 8MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908GR8AVFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Timer Interface Module (TIM1 and TIM2)
17.6.2 Stop Mode
The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect
register conditions or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode
after an external interrupt.
17.7 TIM During Break Interrupts
A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. See
To allow software to clear status bits during a break interrupt, write a 1 to the BCFE bit. If a status bit is
cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state),
software can read and write I/O registers during the break state without affecting status bits. Some status
bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the
break, the bit cannot change during the break state as long as BCFE is at 0. After the break, doing the
second step clears the status bit.
17.8 I/O Signals
Port D shares four of its pins with the TIM. The four TIM channel I/O pins are T1CH0, T1CH1, T2CH0,
and T2CH1 as described in
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.
T1CH0 and T2CH0 can be configured as buffered output compare or buffered PWM pins.
17.9 I/O Registers
These I/O registers control and monitor operation of the TIM:
17.9.1 TIM Status and Control Register
The TIM status and control register (TSC):
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TIM status and control register (TSC)
TIM counter registers (TCNTH:TCNTL)
TIM counter modulo registers (TMODH:TMODL)
TIM channel status and control registers (TSC0 and TSC1)
TIM channel registers (TCH0H:TCH0L, TCH1H:TCH1L)
Enables TIM overflow interrupts
Flags TIM overflows
Stops the TIM counter
Resets the TIM counter
Prescales the TIM counter clock
References to either timer 1 or timer 2 may be made in the following text by
omitting the timer number. For example, TSC may generically refer to both
T1SC AND T2SC.
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
17.3 Pin Name
14.7.3 SIM Break Flag Control
Conventions.
NOTE
Register.
Freescale Semiconductor