R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 163

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

6.3.31
Format
RTS/N
Description
Performs a return from a subroutine procedure. That is, the PC is restored from PR, and
processing is resumed from the address indicated by the PC. This instruction enables a return to
be made from a subroutine procedure called by a BSR or JSR instruction to the origin of the call.
Note
This is not a delayed branch instruction.
Operation
Examples:
RTSN ( )
{
}
TABLE:
TRGET:
PC=PR+4;
RTS/N
Return from Subroutine Procedure with No Delay Slot
/* RTS/N
MOV.L TABLE,R3
JSR/N
ADD
. . . . . . . .
.data.1
. . . . . . . .
NOP
MOV
RTS/N
ReTurn from Subroutine with No delay slot
Abstract
PR → PC
R2,R3
@R3
R0,R1
*/
TRGET
Code
0000000001101011
; R0 = TRGET address
; Branch to TRGET.
; ← Procedure return destination
; Jump table
; ← Entry to procedure
;
; Return to above ADD instruction.
Rev. 3.00 Jul 08, 2005 page 147 of 484
(PR contents)
Section 6 Instruction Descriptions
Branch Instruction
SH-2A/SH2A-FPU (New)
Cycle
3
REJ09B0051-0300
T Bit
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