R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 370

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 Pipeline Operation
When a register (FPUL) that stores the result of a floating-point arithmetic operation instruction is
read (used as a source register) by a following STS instruction, and the value is output to the CPU,
latency is shortened by 2 cycles (figure 8.38).
The time required for the result of an FCMP instruction to be reflected in the T bit is 2 cycles in
the case of single-precision, and 3 cycles in the case of double-precision. As a result, if that
instruction (the following instruction) references the T bit, execution is delayed by the above slot
interval (figure 8.39).
When the FPSCR value is changed using an LDS or LDS.L instruction, execution of the next
instruction by a 3-slot interval (figure 8.40).
Rev. 3.00 Jul 08, 2005 page 354 of 484
REJ09B0051-0300
Figure 8.38 Example of Transferring Result to CPU Immediately Following FPU Operation
Floating-point arithmetic operation
instruction (single-precision)
(FTRC FR0,FPUL)
Next floating-point instruction
(single-precision)
(STS FPUL,R3)
Instruction 1 (single-precision)
(FCMP FR0,FR1)
Instruction 2 (instruction that
(BF)
Instruction 1
(LDS R2,FPSCR)
Instruction 2
(FADD FR4,FR5)
references T bit)
Figure 8.40 Example of Performing FPU Operation Immediately After FPSCR Load
Figure 8.39 Example of Referencing T Bit Immediately After FCMP Instruction
IF
DF
IF
IF
IF
EX
—
DF
IF
DF
IF
NA
—
E1
DF
E1
—
SF
—
E2
EX
E2
ID
DF
SF
NA
EX
E1
E2
SF