R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 332

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 Instruction Descriptions
6.5.18
Description
When FPSCR.PR = 0: Arithmetically subtracts the single-precision floating-point number in FRm
from the single-precision floating-point number in FRn, and stores the result in FRn.
When FPSCR.PR = 1: Arithmetically subtracts the double-precision floating-point number in
DRm from the double-precision floating-point number in DRn, and stores the result in DRn.
When FPSCR.enable.O/U/I is set, an FPU exception trap is generated regardless of whether or not
an exception has occurred. When an exception occurs, correct exception information is reflected in
FPSCR.cause and FPSCR.flag, and FRn or DRn is not updated. Appropriate processing should
therefore be performed by software.
Operation
Rev. 3.00 Jul 08, 2005 page 316 of 484
REJ09B0051-0300
PR
0
1
void FSUB (int m,n)
{
Format
FSUB FRm,FRn
FSUB DRm,DRn DRn-DRm → DRn
pc += 2;
clear_cause();
if((data_type_of(m) == sNaN) ||
else if((data_type_of(m) == qNaN) ||
else switch (data_type_of(m)){
FSUB
Floating-Point
Subtraction
(data_type_of(n) == sNaN)) invalid(n);
case NORM: switch (data_type_of(n)){
(data_type_of(n) == qNaN)) qnan(n);
case NORM:
case PZERO:
case NZERO: register_copy(m,n); FR[n] = -FR[n];break;
default:
Abstract
FRn-FRm → FRn
Floating-point
SUBtract
normal_faddsub(m,n,SUB); break;
break;
Code
1111nnnnmmmm0001 1
1111nnn0mmm00001 6
Floating-Point Instruction
Cycle
T Bit
—