MCF54455CVR200 Freescale Semiconductor, MCF54455CVR200 Datasheet - Page 18

IC MPU 32BIT 200MHZ 360TEPBGA

MCF54455CVR200

Manufacturer Part Number
MCF54455CVR200
Description
IC MPU 32BIT 200MHZ 360TEPBGA
Manufacturer
Freescale Semiconductor
Series
MCF5445xr
Datasheet

Specifications of MCF54455CVR200

Core Processor
Coldfire V4
Core Size
32-Bit
Speed
200MHz
Connectivity
I²C, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, WDT
Number Of I /o
132
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.35 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
360-TEPBGA
Processor Series
MCF544x
Core
ColdFire V4
Data Bus Width
32 bit
Program Memory Size
16 KB
Data Ram Size
32 KB
Interface Type
I2C, SPI, SSI
Maximum Clock Frequency
66 MHz
Number Of Timers
8
Operating Supply Voltage
- 0.3 V to + 4 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
M54455EVB
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit, 16 Channel
On-chip Dac
16 bit, 16 Channel
Leaded Process Compatible
Yes
Rohs Compliant
Yes
Peak Reflow Compatible (260 C)
Yes
For Use With
M54455EVB - BOARD EVAL FOR MCF5445X
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF54455CVR200
Manufacturer:
Freescale Semiconductor
Quantity:
135
Part Number:
MCF54455CVR200
Manufacturer:
FREESCAL
Quantity:
624
Electrical Characteristics
5.2
The average chip-junction temperature (T
Where:
For most applications P
Solving equations 1 and 2 for K gives:
18
1
2
3
4
5
Junction to ambient, natural convection
Junction to ambient (@200 ft/min)
Junction to board
Junction to case
Junction to top of package
Maximum operating junction temperature
T
Q
P
P
P
A
JMA
D
INT
I/O
θ
Freescale recommends the use of θ
device junction temperatures from exceeding the rated specification. System designers should be aware that
device junction temperatures can be significantly influenced by board layout and surrounding devices.
Conformance to the device junction temperature specification can be verified by physical measurement in the
customer’s system using the Ψ
EIA/JESD Standard 51-2.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8.
Board temperature is measured on the top surface of the board near the package.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL
SPEC-883 Method 1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written in conformance with Psi-JT.
JMA
Thermal Characteristics
and Ψ
= Ambient Temperature, °C
= Package Thermal Resistance, Junction-to-Ambient, °C/W
= P
= I
= Power Dissipation on Input and Output Pins — User Determined
jt
parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection.
I/O
INT
DD
< P
× IV
+ P
Characteristic
INT
I/O
DD
MCF5445x ColdFire
and can be ignored. An approximate relationship between P
, Watts - Chip Internal Power
K
jt
J
parameter, the device power dissipation, and the method described in
) in °C can be obtained from:
=
Table 6. Thermal Characteristics
P
JmA
D
T
J
×
P
and power dissipation specifications in the system design to prevent
(
Four layer board
Four layer board
=
D
T
T
A
=
®
A
×
(2s2p)
(2s2p)
-------------------------------- -
(
Microprocessor Data Sheet, Rev. 6
+
T
273°C
(
J
P
+
D
K
273°C
×
)
Θ
+
JMA
Q
)
JMA
)
Symbol
θ
θ
θ
θ
×
Ψ
JMA
T
JC
JA
JB
P
jt
j
2
D
MAPBGA
29
25
256
2
105
18
10
1,5
1,2
1,2
3
4
D
and T
TEPBGA
Freescale Semiconductor
J
24
21
360
2
105
15
11
(if P
1,5
1,2
1,2
3
4
I/O
is neglected) is:
°C / W
°C / W
°C / W
°C / W
°C / W
Unit
o
C
Eqn. 1
Eqn. 2
Eqn. 3

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