LT1121CS8-5#PBF Linear Technology, LT1121CS8-5#PBF Datasheet - Page 11

• Manufacturer Part Number: LT1121CS8-5#PBF
• Description: IC REG LDO 5V 150MA 8-SOIC
• Manufacturer: Linear Technology

Specifications of LT1121CS8-5#PBF

• Regulator Topology: Positive Fixed
• Voltage - Output: 5V
• Voltage - Input: Up to 30V
• Voltage - Dropout (typical): 0.42V @ 150mA
• Number Of Regulators: 1
• Current - Output: 150mA
• Operating Temperature: 0°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Primary Input Voltage: 30V
• Output Voltage Fixed: 5V
• Dropout Voltage Vdo: 420mV
• No. Of Pins: 8
• Output Current: 150mA
• Operating Temperature Range: 0°C To +125°C
• Msl: MSL 1 - Unlimited
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Limit (min): -

APPLICATIO S I FOR ATIO
spike while charging the sample-and-hold capacitors at
the end of conversion. During conversion, the analog
inputs draw only a small leakage current. If the source
impedance of the driving circuit is low, then the LTC1608
inputs can be driven directly. As source impedance in-
creases so will acquisition time (see Figure 10). For
minimum acquisition time with high source impedance, a
buffer amplifier should be used. The only requirement is
that the amplifier driving the analog input(s) must settle
after the small current spike before the next conversion
starts (settling time must be 200ns for full throughput
rate).
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a
low output impedance (< 100 ) at the closed-loop band-
width frequency. For example, if an amplifier is used in a
gain of +1 and has a unity-gain bandwidth of 50MHz, then
RD = CONVST
RD = CONVST
CS = 0
BUSY
DATA
U
CS = 0
BUSY
DATA
U
t
6
t
10
t
6
W
t
10
DATA (N – 1)
D15 TO D0
Figure 8. Mode 2. Slow Memory Mode Timing
t
CONV
DATA (N – 1)
D15 TO D0
t
CONV
U
t
11
Figure 9. ROM Mode Timing
t
7
D15 TO D0
DATA N
t
11
the output impedance at 50MHz should be less than
100 . The second requirement is that the closed-loop
bandwidth must be greater than 15MHz to ensure
adequate small-signal settling for full throughput rate. If
slower op amps are used, more settling time can be
provided by increasing the time between conversions.
t
t
8
8
0.01
0.1
10
Figure 10. t
1
1
D15 TO D0
DATA N
D15 TO D0
10
SOURCE RESISTANCE ( )
DATA N
ACQ
vs Source Resistance
100
DATA (N + 1)
D15 TO D0
1k
1608 F09
1608 F10
LTC1608
1608 F08
10k
11