LT1121CS8-5#PBF Linear Technology, LT1121CS8-5#PBF Datasheet - Page 5

IC REG LDO 5V 150MA 8-SOIC

LT1121CS8-5#PBF

Manufacturer Part Number
LT1121CS8-5#PBF
Description
IC REG LDO 5V 150MA 8-SOIC
Manufacturer
Linear Technology
Datasheets

Specifications of LT1121CS8-5#PBF

Regulator Topology
Positive Fixed
Voltage - Output
5V
Voltage - Input
Up to 30V
Voltage - Dropout (typical)
0.42V @ 150mA
Number Of Regulators
1
Current - Output
150mA
Operating Temperature
0°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Primary Input Voltage
30V
Output Voltage Fixed
5V
Dropout Voltage Vdo
420mV
No. Of Pins
8
Output Current
150mA
Operating Temperature Range
0°C To +125°C
Msl
MSL 1 - Unlimited
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Limit (min)
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LT1121CS8-5#PBFLT1121CS8-5
Manufacturer:
LINEAR/凌特
Quantity:
20 000
Company:
Part Number:
LT1121CS8-5#PBFLT1121CS8-5#TRPBF
Manufacturer:
LINEAR
Quantity:
14 951
Note 4: When these pin voltages are taken below V
by internal diodes. This product can handle input currents greater than
100mA below V
Note 5: V
otherwise specified.
Note 6: Linearity, offset and full-scale specification apply for a single-
ended A
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Typical RMS noise at the code transitions.
Note 9: Bipolar offset is the offset voltage measured from – 0.5LSB when
the output code flickers between 0000 0000 0000 0000 and 1111 1111
1111 1111.
TYPICAL PERFOR A CE CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
–0.5
–1.0
–1.5
–2.0
100
2.0
1.5
1.0
0.5
90
80
70
60
50
40
30
20
10
–32768
0
0
1k
Integral Nonlinearity
vs Output Code
Signal-to-Noise Ratio
vs Input Frequency
IN
DD
+
input with A
= 5V, V
–16384
SS
without latchup. These pins are not clamped to V
10k
SS
FREQUENCY (Hz)
= – 5V, f
IN
CODE
0
grounded.
SMPL
100k
16384
= 500kHz, and t
W
1608 G01
1608 G04
32767
U
1M
SS
r
, they will be clamped
= t
–0.2
–0.4
–0.6
–1.0
–100
–110
–0.8
f
0.2
–10
–20
–30
–40
–50
–60
–70
–80
–90
1.0
0.8
0.6
0.4
= 5ns unless
–32768
0
0
1k
Differential Nonlinearity
vs Output Code
Distortion vs Input Frequency
DD
–16384
.
INPUT FREQUENCY (Hz)
10k
CODE
0
Note 10: Signal-to-Noise Ratio (SNR) is measured at 5kHz and distortion
is measured at 100kHz. These results are used to calculate Signal-to-Nosie
Plus Distortion (SINAD).
Note 11: Guaranteed by design, not subject to test.
Note 12: Recommended operating conditions.
Note 13: The falling CONVST edge starts a conversion. If CONVST returns
high at a critical point during the conversion it can create small errors. For
best performance ensure that CONVST returns high either within 250ns
after conversion start or after BUSY rises.
Note 14: The acquisition time would go up to 400ns and the conversion
time would go up to 1.8 s. However, the throughput time (acquisition +
conversion) is guaranteed by test to be 2 s max.
Note 15: If RD precedes CS , the output enable will be gated by CS .
100k
16384
1608 G02
THD
3RD
2ND
1608 G05
32767
1M
–100
–110
100
–10
–20
–30
–40
–50
–60
–70
–80
–90
90
80
70
60
50
40
30
20
10
0
0
1k
1k
S/(N + D) vs Input Frequency
and Amplitude
Spurious-Free Dynamic Range
vs Input Frequency
INPUT FREQUENCY (Hz)
10k
10k
FREQUENCY (Hz)
V
V
V
IN
IN
IN
= –20dB
= –40dB
= 0dB
LTC1608
100k
100k
1608 G03
1608 G06
5
1M
1M

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