MC9328MX1DVM20 Freescale Semiconductor, MC9328MX1DVM20 Datasheet - Page 88

• Manufacturer Part Number: MC9328MX1DVM20
• Description: IC MCU I.MX 200MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX1r

Specifications of MC9328MX1DVM20

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 110
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 1.7 V ~ 3.3 V
• Oscillator Type: External
• Operating Temperature: -30°C ~ 70°C
• Package / Case: 256-MAPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

1
2
3
Functional Description and Application Information
88
Ref No.
All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
There are 2 sets of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad 261) and Port B
alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they can be viewed both at Port C primary
function and Port B alternate function. When SSI signals are configured as input, the SSI module selects the input based on
status of the FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary
function.
bl = bit length; wl = word length.
27a
27b
18
19
20
21
22
23
24
25
26
28
29
30
31
32
33
34
STCK high to STFS (bl) high
SRCK high to SRFS (bl) high
STCK high to STFS (bl) low
SRCK high to SRFS (bl) low
STCK high to STFS (wl) high
SRCK high to SRFS (wl) high
STCK high to STFS (wl) low
SRCK high to SRFS (wl) low
STCK high to STXD valid from high impedance
STCK high to STXD high
STCK high to STXD low
STCK high to STXD high impedance
SRXD setup time before SRCK low
SRXD hole time after SRCK low
SRXD setup before STCK falling
SRXD hold after STCK falling
SRXD setup before STCK falling
SRXD hold after STCK falling
Table 39. SSI (Port C Primary Function) Timing Parameter Table (Continued)
Synchronous External Clock Operation (Port C Primary Function
Synchronous Internal Clock Operation (Port C Primary Function
Parameter
3
3
3
3
3
3
3
3
MC9328MX1 Technical Data, Rev. 7
Minimum
18.01
18.47
8.98
9.12
1.14
15.4
1.14
–
–
–
–
–
–
–
–
0
0
0
1.8 ± 0.1 V
Maximum
28.16
18.13
18.24
92.8
92.8
92.8
92.8
92.8
92.8
92.8
92.8
28.5
–
–
–
–
–
–
Minimum
15.8
16.2
13.5
2
7.0
8.0
1.0
1.0
2
)
0
0
0
0
0
0
0
0
0
0
0
)
3.0 ± 0.3 V
Freescale Semiconductor
Maximum
81.4
81.4
81.4
81.4
81.4
81.4
81.4
81.4
24.7
15.9
16.0
25.0
–
–
–
–
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns