AD9856/PCB Analog Devices Inc, AD9856/PCB Datasheet - Page 25

• Manufacturer Part Number: AD9856/PCB
• Description: BOARD EVAL FOR AD9856
• Manufacturer: Analog Devices Inc
• Type: DDS Modulatorsr

Specifications of AD9856/PCB

• Rohs Status: RoHS non-compliant
• For Use With/related Products: AD9856
• Lead Free Status / RoHS Status: Not Compliant

Figure 43 shows the effectiveness of the ISF in correcting for
the SINC distortion. The plot includes a graph of the SINC
envelope, the ISF response and the SYSTEM response (which is
the product of the SINC and ISF responses). Note that the ISF
exhibits an insertion loss of 3.1 dB. Thus, signal levels at the
output of the AD9856 with the ISF bypassed are 3.1 dB higher
than with the ISF engaged. For modulated output signals,
however, which have a relatively wide bandwidth, the benefits
of the SINC compensation usually outweigh the 3 dB loss in
output level. The decision of whether to use the ISF is an
application specific system design issue.
DIRECT DIGITAL SYNTHESIZER FUNCTION
The direct digital synthesizer (DDS) block generates the sine/
cosine carrier reference signals that are digitally modulated by
the I/Q data paths. The DDS function is frequency tuned via
the serial control port with a 32-bit tuning word. This allows the
AD9856’s output carrier frequency to be very precisely tuned
while still providing output frequency agility.
The equation relating output frequency of the AD9856 digital
modulator to the frequency tuning word (FTWORD) and the
system clock (SYSCLK) is given as:
where A
a decimal number from 0 to 4,294,967,296 (2
For example, find the FTWORD for A
SYSCLK = 122.88 MHz.
If A
Loading 556AAAABh into control bus registers 02h–05h
(for Profile 1) programs the AD9856 for A
given a SYSCLK frequency of 122.88 MHz.
OUT
FTWORD 556
–1
–2
–3
–4
A
4
3
2
1
0
OUT
= 41 MHz and SYSCLK = 122.88 MHz, then:
0
OUT
=
and SYSCLK frequencies are in Hz and FTWORD is
(
FTWORD
FREQUENCY NORMALIZED TO SAMPLE RATE
=
Figure 43. Inverse SINC Filter Response
0.1
AAAAB
×
SYSCLK
0.2
hex
)
2 /
32
0.3
SYSTEM
OUT
SINC
ISF
= 41 MHz and
OUT
0.4
31
= 41 MHz,
).
0.5
Rev. C | Page 25 of 36
A Technical Tutorial on Digital Signal Synthesis is available on
the Analog Devices website at:
http://www.analog.com/UploadedFiles/Tutorials/450968421DD
S_Tutorial_rev12-2-99.pdf
The tutorial provides basic applications information for a
variety of digital synthesis implementations, as well as a detailed
explanation of aliases.
D/A CONVERTER
A 12-bit digital-to-analog converter (DAC) is used to convert
the digitally processed waveform into an analog signal. The
worst-case spurious signals due to the DAC are the harmonics
of the fundamental signal and their aliases (see the AD9851
Complete-DDS data sheet for a details about aliased images).
The wideband 12-bit DAC in the AD9856 maintains spurious-
free dynamic range (SFDR) performance of −60 dBc up to
A
The conversion process produces aliased components of the
fundamental signal at n × SYSCLK ± F
are typically filtered with an external RLC filter at the DAC
output. It is important for this analog filter to have a sufficiently
flat gain and linear phase response across the bandwidth of
interest to avoid modulation impairments. An inexpensive
seventh-order elliptical low-pass filter is sufficient to suppress
the aliased components for HFC network applications.
The AD9856 provides true and complement current outputs on
pins 30 and 29, respectively. The full-scale output current is set
by the R
I
For example, if a full-scale output current of 20 mA is desired,
then R
doubling of the R
output current is specified as 20 mA.
The full-scale output current range of the AD9856 is 5 mA to
20 mA. Full-scale output currents outside of this range degrade
SFDR performance. SFDR is also slightly affected by output
matching, that is, the two outputs should be terminated equally
for best SFDR performance.
The output load should be located as close as possible to the
AD9856 package to minimize stray capacitance and inductance.
The load may be a simple resistor to ground, an op amp
current-to-voltage converter, or a transformer-coupled circuit.
It is best not to attempt to directly drive highly reactive loads
(such as an LC filter). Driving an LC filter without a
transformer requires that the filter be doubly terminated for
best performance, that is, the filter input and output should
both be resistively terminated with the appropriate values. The
parallel combination of the two terminations determines the
OUT
OUT
is determined by
= 42 MHz and −55 dBc up to A
R
SET
SET
SET
= (39.936/0.02), or approximately 2 kΩ. Every
=
resistor at Pin 25. The value of R
39.936/
SET
I
OUT
value halves the output current. Maximum
OUT
CARRIER
= 65 MHz.
SET
(n = 1, 2, 3). These
for a particular
AD9856