AD9856/PCB Analog Devices Inc, AD9856/PCB Datasheet - Page 26

• Manufacturer Part Number: AD9856/PCB
• Description: BOARD EVAL FOR AD9856
• Manufacturer: Analog Devices Inc
• Type: DDS Modulatorsr

Specifications of AD9856/PCB

• Rohs Status: RoHS non-compliant
• For Use With/related Products: AD9856
• Lead Free Status / RoHS Status: Not Compliant

AD9856
load that the AD9856 sees for signals within the filter pass
band. For example, a 50 Ω terminated input/output low-pass
filter looks like a 25 Ω load to the AD9856.
The output compliance voltage of the AD9856 is −0.5 V to
+1.5 V. Any signal developed at the DAC output should not
exceed +1.5 V, otherwise, signal distortion results. Furthermore,
the signal may extend below ground as much as 0.5 V without
damage or signal distortion. The use of a transformer with a
grounded center tap for common-mode rejection results in
signals at the AD9856 DAC output pins that are symmetrical
about ground.
As previously mentioned, by differentially combining the two
signals the user can provide some degree of common-mode
signal rejection. A differential combiner might consist of a
transformer or an op amp. The object is to combine or amplify
only the difference between two signals and to reject any
common, usually undesirable, characteristic, such as 60 Hz
hum or clock feedthrough that is equally present on both input
signals. The AD9856 true and complement outputs can be
differentially combined using a broadband 1:1 transformer with
a grounded, center-tapped primary to perform differential
combining of the two DAC outputs.
REFERENCE CLOCK MULTIPLIER
Because the AD9856 is a DDS-based modulator, a relatively
high frequency system clock is required. For DDS applications,
the carrier is typically limited to about 40% of SYSCLK. For a
65 MHz carrier, the system clock required is above 160 MHz. To
avoid the cost associated with these high frequency references
and the noise coupling issues associated with operating a high
frequency clock on a PC board, the AD9856 provides an on-
chip programmable clock multiplier (REFCLK multiplier). The
available clock multiplier range is from 4× to 20×, in integer
steps. With the REFCLK multiplier enabled, the input reference
clock required for the AD9856 can be kept in the 10 MHz to
50 MHz range for 200 MHz system operation, which results in
cost and system implementation savings. The REFCLK mult-
iplier function maintains clock integrity as evidenced by the
AD9856’s system phase noise characteristics of −105 dBc/Hz
(A
virtually no clock related spurii in the output spectrum.
External loop filter components consisting of a series resistor
(1.3 kΩ) and capacitor (0.01 µF) provide the compensation zero
for the REFCLK multiplier PLL loop. The overall loop perform-
ance has been optimized for these component values.
THROUGHPUT AND LATENCY
Data latency through the AD9856 is easiest to describe in terms
of SYSCLK clock cycles. Latency is a function of the AD9856
configuration primarily affected by the CIC interpolation rate
and whether the third half-band filter is engaged.
OUT
= 40 MHz, REFCLK multiplier = 6, Offset = 1 kHz) and
Rev. C | Page 26 of 36
When the third half-band filter is engaged, the AD9856 latency
is given by 126 N + 37 SYSCLK clock cycles, where N is the CIC
interpolation rate.
If the AD9856 is configured to bypass the third half-band filter,
the latency is given by 63 N + 37 SYSCLK clock cycles.
These equations should be considered estimates, as observed
latency may be data dependent. The latency was calculated
using the linear delay model for the FIR filters.
In single-tone mode, frequency hopping is accomplished via
changing the PROFILE input pins. The time required to switch
from one frequency to another is < 50 SYSCLK cycles with the
inverse SINC filter engaged. With the inverse SINC filter
bypassed, the latency drops to < 35 SYSCLK cycles.
CONTROL INTERFACE
The flexible AD9856 synchronous serial communications
port allows easy interface to many industry standard micro-
controllers and microprocessors. The serial I/O is compatible
with most synchronous transfer formats, including the
Motorola 6905/11 SPI® and Intel® 8051 SSR protocols.
The interface allows read/write access to all registers that
configure the AD9856. Single or multiple byte transfers are
supported, as well as MSB first or LSB first transfer formats.
The AD9856’s serial interface port can be configured as a
single-pin I/O (SDIO) or two unidirectional pins for
input/output (SDIO/SDO).
GENERAL OPERATION OF THE SERIAL INTERFACE
There are two phases to a communication cycle with the
AD9856. Phase 1 is the instruction cycle, which is the writing of
an instruction byte into the AD9856, coincident with the first
eight SCLK rising edges. The instruction byte provides the
AD9856 serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication
cycle. The Phase 1 instruction byte defines whether the
upcoming data transfer is read or write, the number of bytes in
the data transfer (1 to 4), and the starting register address for
the first byte of the data transfer.
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the AD9856. The
remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9856
and the system controller. Phase 2 of the communication cycle
is a transfer of 1, 2, 3, or 4 data bytes as determined by the
instruction byte. Normally, using one communication cycle in a
multibyte transfer is the preferred method. However, single-byte
communication cycles are useful to reduce CPU overhead when
register access requires one byte only. Examples of this may be
to write the AD9856 SLEEP bit, or an AD8320/AD8321 gain
control byte.