AD9856/PCB Analog Devices Inc, AD9856/PCB Datasheet - Page 27

• Manufacturer Part Number: AD9856/PCB
• Description: BOARD EVAL FOR AD9856
• Manufacturer: Analog Devices Inc
• Type: DDS Modulatorsr

Specifications of AD9856/PCB

• Rohs Status: RoHS non-compliant
• For Use With/related Products: AD9856
• Lead Free Status / RoHS Status: Not Compliant

At the completion of any communication cycle, the AD9856
serial port controller expects the next eight rising SCLK edges
to be the instruction byte of the next communication cycle.
All data input to the AD9856 is registered on the rising edge
of SCLK. All data is driven out of the AD9856 on the falling
edge of SCLK. Figure 44 through Figure 47 show the general
operation of the AD9856 serial port.
INSTRUCTION BYTE
The instruction byte contains the following information as
shown in Table 7.
Table 7. Instruction Byte Information
MSB
R/W
D6
N1
D5
N0
SCLK
SCLK
SCLK
SCLK
SDIO
SDIO
SDIO
SDIO
SDO
CS
CS
CS
CS
D4
A4
I
I
7
7
I
I
D3
A3
7
7
I
I
6
6
I
I
6
6
INSTRUCTION CYCLE
INSTRUCTION CYCLE
INSTRUCTION CYCLE
INSTRUCTION CYCLE
I
I
D2
A2
5
5
Figure 45. Three-Wire Serial Port Read Timing—Clock Stall Low
I
Figure 47. Two-Wire Serial Port Read Timing—Clock Stall High
5
I
5
I
I
Figure 44. Serial Port Writing Timing—Clock Stall Low
4
4
Figure 46. Serial Port Write Timing—Clock Stall High
I
4
I
4
D1
A1
I
I
3
3
I
I
3
3
I
I
2
2
I
2
I
LSB
A0
2
Rev. C | Page 27 of 36
I
I
1
1
I
1
I
1
I
I
0
0
I
0
I
0
D
D
O 7
7
D
R/ W —Bit 7 determines whether a read or write data transfer
occurs after the instruction byte write. Logic high indicates a
read operation. Logic zero indicates a write operation.
N1, N0—Bits 6 and 5 of the instruction byte determine the
number of bytes to be transferred during the data transfer cycle
of the communications cycle. Table 8 shows the decode bits.
Table 8. N1, N0 Decode Bits
N1
0
0
1
1
A4, A3, A2, A1, A0—Bits 4, 3, 2, 1, 0 of the instruction byte
determine which register is accessed during the data transfer
portion of the communications cycle. For multibyte transfers,
this address is the starting byte address. The remaining register
addresses are generated by the AD9856.
7
D
O 7
D
D
6
O 6
D
D
O 6
6
D
D
DATA TRANSFER CYCLE
DATA TRANSFER CYCLE
DATA TRANSFER CYCLE
DATA TRANSFER CYCLE
5
DON'T CARE
O 5
D
D
5
O 5
N0
0
1
0
1
D
D
4
O 4
D
D
4
O 4
D
D
3
O 3
D
D
3
O 3
D
D
2
O 2
D
D
Description
Transfer 1 byte
Transfer 2 bytes
Transfer 3 bytes
Transfer 4 bytes
2
O 2
D
D
1
O 1
D
D
1
O 1
D
0
D
D
O 0
O 0
D
0
AD9856