AD9856/PCB Analog Devices Inc, AD9856/PCB Datasheet - Page 7

• Manufacturer Part Number: AD9856/PCB
• Description: BOARD EVAL FOR AD9856
• Manufacturer: Analog Devices Inc
• Type: DDS Modulatorsr

Specifications of AD9856/PCB

• Rohs Status: RoHS non-compliant
• For Use With/related Products: AD9856
• Lead Free Status / RoHS Status: Not Compliant

Table 4. Functional Block Mode Descriptions
Functional Block
Operating Modes
Input Data Format
Input Sample Rate
Input Reference
Clock Frequency
Internal Reference
Clock Multiplier
Profile Select
Interpolating Range
Half-Band Filters
TxENABLE Function–
Burst Mode
TxENABLE Function–
Continuous Mode
Inverse SINC Filter
I/Q Channel Invert
Full Sleep Mode
Mode Description
1. Complex quadrature modulator mode.
2. Single-tone output mode.
Programmable: 12-bit, 6-bit, or 3-bit input formats. Data input to the AD9856 is 12-bit, twos complement. Complex
I/Q symbol component data is required to be at least 2× oversampled, depending upon configuration.
Up to 50 Msamples/sec @ 200 MHz SYSCLK rate.
For DC to 80 MHz A
programmable via control bus; with REFCLK multiplier disabled: 200 MHz.
Note: For optimum data synchronization, the AD9856 reference clock and the input data clock should be derived
from the same clock source.
Programmable in integer steps over the range of 4× to 20×. Can be disabled (effective REFCLK multiplier = 1) via
control bus. Output of REFCLK multiplier = SYSCLK rate, which is the internal clock rate applied to the DDS and DAC
function.
Four pin-selectable, preprogrammed formats. Available for modulation and single-tone operating modes.
Fixed 4×, selectable 2×, and selectable 2× to 63× range.
Interpolating filters that provide upsampling and reduce the effects of the CIC passband roll-off characteristics.
When burst mode is enabled via the control bus, the rising edge of the applied TxENABLE pulse should be
coincident with, and frame, the input data packet. This establishes data sampling synchronization.
When continuous mode is enabled via the control bus, the TxENABLE pin becomes an I/Q control line. A Logic 1
on TxENABLE indicates I data is being presented to the AD9856. A Logic 0 on TxENABLE indicates Q data is being
presented to the AD9856. Each rising edge of TxENABLE resynchronizes the AD9856 input sampling capability.
Precompensates for SIN(x)/x roll-off of DAC; user bypassable.
[I ×Cos(ωt) + Q ×Sin(ωt)] or [I ×Cos(ωt) − Q ×Sin(ωt)] (default), configurable via control bus, per profile.
Power dissipation reduced to less than 6 mW when full sleep mode is active; programmable via the control bus.
OUT
operation (200 MHz SYSCLK rate) with REFCLK multiplier enabled: 10 MHz to50 MHz,
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AD9856