AD9856/PCB Analog Devices Inc, AD9856/PCB Datasheet - Page 28

• Manufacturer Part Number: AD9856/PCB
• Description: BOARD EVAL FOR AD9856
• Manufacturer: Analog Devices Inc
• Type: DDS Modulatorsr

Specifications of AD9856/PCB

• Rohs Status: RoHS non-compliant
• For Use With/related Products: AD9856
• Lead Free Status / RoHS Status: Not Compliant

AD9856
SERIAL INTERFACE PORT PIN DESCRIPTIONS
SCLK—Serial Clock
The serial clock pin is used to synchronize data to and from the
AD9856 and to run the internal state machines. SCLK
maximum frequency is 10 MHz.
CS —Chip Select
Active low input that allows more than one device on the same
serial communications lines. The SDO and SDIO pins go to a
high impedance state when this input is high. If driven high
during any communications cycle, that cycle is suspended until
CS is reactivated low. Chip Select can be tied low in systems that
maintain control of SCLK.
SDIO—Serial Data I/O
Data is always written into the AD9856 on this pin. However,
this pin can be used as a bidirectional data line. The config-
uration of this pin is controlled by Bit 7 of register address 0h.
The default is Logic 0, which configures the SDIO pin as
bidirectional.
SDO—Serial Data Out
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. In the case where the
AD9856 operates in a single bidirectional I/O mode, this pin
does not output data and is set to a high impedance state.
SYNC I/O
Synchronizes the I/O port state machines without affecting the
addressable registers contents. An active high input on the
SYNC I/O pin causes the current communication cycle to abort.
After SYNC I/O returns low (Logic 0), another communication
cycle may begin, starting with the instruction byte write.
CA CLK
Output clock pin to the AD8320/AD8321. If using the AD9856
to control the AD8320/AD8321 programmable cable driver
amplifier, connect this pin to the CLK input of the AD8320/
AD8321.
CA DATA
Output data pin to the AD8320/AD8321. If using the AD9856
to control the AD8320/AD8321 programmable cable driver
amplifier, connect this pin to the SDATA input of the AD8320/
AD8321.
CA ENABLE
Output Enable pin to the AD8320/AD8321. If using the
AD9856 to control the AD8320/AD8321 programmable cable
driver amplifier, connect this pin to the DATEN input of the
AD8320/AD8321.
MSB/LSB TRANSFERS
The AD9856 serial port can support both MSB-first or LSB-first
data formats. This functionality is controlled by the REG0<6>
bit. The default value of REG0<6> is low (MSB first). When
Rev. C | Page 28 of 36
REG0<6> is set active high, the AD9856 serial port is in LSB
first format. The instruction byte must be written in the format
indicated by REG0<6>. That is, if the AD9856 is in LSB-first
mode, the instruction byte must be written from least
significant bit to most significant bit. Multibyte data transfers in
MSB format can be completed by writing an instruction byte
that includes the register address of the most significant byte. In
MSB-first mode, the serial port internal byte address generator
decrements for each byte required of the multibyte commun-
ication cycle. Multibyte data transfers in LSB-first format can be
completed by writing an instruction byte that includes the
register address of the least significant byte. In LSB-first mode,
the serial port internal byte address generator increments for
each byte required of the multibyte communication cycle.
NOTES ON SERIAL PORT OPERATION
The AD9856 serial port configuration bits reside in Bit 6 and
Bit 7 of register address 0h. It is important to note that the
configuration changes immediately upon writing to this
register. For multibyte transfers, writing to this register may
occur during the middle of a communication cycle. Care must
be taken to compensate for this new configuration for the
remainder of the current communication cycle.
The AD9856 serial port controller address can roll from 19h to
0h for multibyte I/O operations if the MSB-first mode is active.
The serial port controller address can roll from 0h to 19h for
multibyte I/O operations if the LSB-first mode is active.
The system must maintain synchronization with the AD9856
or the internal control logic is not able to recognize further
instructions. For example, if the system sends an instruction
byte for a 2-byte write, then pulses the SCLK pin for a 3-byte
write (24 additional SCLK rising edges), communication
synchronization is lost. In this case, the first 16 SCLK rising
edges after the instruction cycle properly write the first two data
bytes into the AD9856, but the next eight rising SCLK edges are
interpreted as the next instruction byte, not the final byte of the
previous communication cycle.
In the case where synchronization is lost between the system
and the AD9856, the SYNC I/O pin provides a means to
reestablish synchronization without reinitializing the entire
chip. The SYNC I/O pin enables the user to reset the AD9856
state machine to accept the next eight SCLK rising edges to be
coincident with the instruction phase of a new communication
cycle. By applying and removing a high signal to the SYNC I/O
pin, the AD9856 is set to once again begin performing the
communication cycle in synchronization with the system. Any
information that had been written to the AD9856 registers
during a valid communication cycle prior to loss of
synchronization remains intact.