SI4330-B1-FM Silicon Laboratories Inc, SI4330-B1-FM Datasheet - Page 33

IC RCVR ISM 960MHZ 3.6V 20-QFN

SI4330-B1-FM

Manufacturer Part Number
SI4330-B1-FM
Description
IC RCVR ISM 960MHZ 3.6V 20-QFN
Manufacturer
Silicon Laboratories Inc
Type
ISM Receiverr
Datasheets

Specifications of SI4330-B1-FM

Package / Case
20-QFN
Frequency
960MHz
Sensitivity
-118dBm
Data Rate - Maximum
128kbps
Modulation Or Protocol
FSK, GFSK, OOK
Current - Receiving
18.5mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Voltage - Supply
1.8 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Operating Frequency
240 MHz to 960 MHz
Operating Supply Voltage
3 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Current
18.5 mA
Package
20QFN EP
Maximum Data Rate
256 Kbps
Transmission Media Type
Wireless
Power Supply Type
Analog
Typical Operating Supply Voltage
3 V
Minimum Operating Supply Voltage
1.8 V
Maximum Operating Supply Voltage
3.6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Applications
-
Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1629-5
SI4330-V2-FM

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI4330-B1-FM
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Company:
Part Number:
SI4330-B1-FM
Quantity:
75
Part Number:
SI4330-B1-FM-02T
Manufacturer:
SILICON
Quantity:
112
Part Number:
SI4330-B1-FMR
Manufacturer:
HIROSE
Quantity:
3 200
Part Number:
SI4330-B1-FMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
6.2. Packet Configuration
When using the FIFO, automatic packet handling may be enabled for the RX mode. "Register 30h. Data Access
Control" through “Register 39h. Synchronization Word 0,” on page 99 and “Register 3Fh. Check Header 3,” on
page 100 through “Register 4Bh. Received Packet Length,” on page 104 control the configuration, status, and
decoded RX packet data for Packet Handling.
The general packet structure is shown in Figure 12. The length of each field is shown below the field. The preamble
pattern is always a series of alternating ones and zeroes, starting with a zero. All the fields have programmable
lengths to accommodate different applications. The most common CRC polynominals are available for selection.
An overview of the packet handler configuration registers is shown in Table 13.
6.3. Packet Handler RX Mode
6.3.1. Packet Handler Disabled
When the packet handler is disabled certain fields in the received packet are still required. Proper modem
operation requires preamble and sync when the FIFO is being used, as shown in Figure 14. Bits after sync will be
treated as raw data with no qualification. This mode allows for the creation of a custom packet handler when the
automatic qualification parameters are not sufficient. Manchester encoding is supported but data whitening, CRC,
and header checks are not
6.3.2. Packet Handler Enabled
When the packet handler is enabled, all the fields of the packet structure need to be configured. The receive FIFO
can be configured to handle packets of fixed or variable length with or without a header. If multiple packets are
desired to be stored in the FIFO, then there are options available for the different fields that will be stored into the
FIFO. Figure 15 demonstrates the options and settings available when multiple packets are enabled. Figure 16
demonstrates the operation of fixed packet length and correct/incorrect packets.
Figure 12. Required RX Packet Structure with Packet Handler Disabled
Preamble
1- 512 Bytes
Preamble
1-4 Bytes
Figure 11. Packet Structure
SYNC
Rev 1.0
Data
DATA
0 or 2
Bytes
Si4330-B1
CRC
33

Related parts for SI4330-B1-FM