SI4330-B1-FM Silicon Laboratories Inc, SI4330-B1-FM Datasheet - Page 55

• Manufacturer Part Number: SI4330-B1-FM
• Description: IC RCVR ISM 960MHZ 3.6V 20-QFN
• Manufacturer: Silicon Laboratories Inc
• Type: ISM Receiverr

Specifications of SI4330-B1-FM

• Package / Case: 20-QFN
• Frequency: 960MHz
• Sensitivity: -118dBm
• Data Rate - Maximum: 128kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Current - Receiving: 18.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 240 MHz to 960 MHz
• Operating Supply Voltage: 3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 18.5 mA
• Package: 20QFN EP
• Maximum Data Rate: 256 Kbps
• Transmission Media Type: Wireless
• Power Supply Type: Analog
• Typical Operating Supply Voltage: 3 V
• Minimum Operating Supply Voltage: 1.8 V
• Maximum Operating Supply Voltage: 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Applications: -
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1629-5; SI4330-V2-FM

3A-3E
4C-4E
6A-6C
50-5F
63-68
Add
2C
2D
28
29
2A
2B
2E
2F
30
31
32
33
34
35
36
37
38
39
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4F
60
61
62
69
70
71
73
74
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
Crystal Oscillator/Control Test
Antenna Diversity Register 1
Antenna Diversity Register 2
Preamble Detection Control
Modulation Mode Control 1
Modulation Mode Control 2
Channel Filter Coefficient
Received Packet Length
OOK Counter Value 1
OOK Counter Value 2
AFC Correction Read
Data Access Control
Received Header 3
Received Header 2
Received Header 1
Received Header 0
Frequency Offset 1
Frequency Offset 2
Header Control 1
Header Control 2
Preamble Length
Header Enable 3
Header Enable 2
Header Enable 1
Header Enable 0
Slicer Peak Hold
Check Header 3
Check Header 2
Check Header 1
Check Header 0
AGC Override 1
Function/Desc
EzMAC status
ADC8 Control
Sync Word 3
Sync Word 2
Sync Word 1
Sync Word 0
AFC Limiter
Address
Inv_pre_th[3]
Table 17. Register Descriptions (Continued)
afc_corr[9]
afc_corr[9]
prealen[7]
adrssi1[7]
adrssib[7]
Reserved
Reserved
Reserved
Reserved
Reserved
ookcnt[7]
preath[4]
hden[31]
hden[23]
hden[15]
Afclim[7]
sync[31]
sync[23]
sync[15]
chhd[31]
chhd[23]
chhd[15]
rxplen[7]
enpacrx
rxhd[31]
rxhd[23]
rxhd[15]
skipsyn
hden[7]
sync[7]
chhd[7]
pwst[2]
rxhd[7]
trclk[1]
fo[7]
D7
0
Inv_pre_th[2] Inv_pre_th[1] Inv_pre_th[0]
afc_corr[8]
afc_corr[9]
prealen[6]
adrssia[6]
adrssib[6]
Reserved
Reserved
Reserved
ookcnt[6]
preath[3]
hden[30]
hden[22]
hden[14]
Afclim[6]
attack[2]
sync[30]
sync[22]
sync[14]
chhd[30]
chhd[22]
chhd[14]
rxplen[6]
hdlen[2]
rxhd[30]
rxhd[22]
rxhd[14]
hden[6]
sync[6]
chhd[6]
pwst[1]
rxhd[6]
trclk[0]
lsbfrst
rxcrc1
fo[6]
D6
sgi
bcen[3:0]
Rev 1.0
afc_corr[7]
adrssia[5]
adrssib[5]
prealen[5]
preath[2]
Reserved
ookcnt[5]
Afclim[5]
ookfrzen
attack[1]
chhd[29]
chhd[21]
chhd[13]
hden[29]
hden[21]
hden[13]
rxplen[5]
dtmod[1]
crcdonly
sync[29]
sync[21]
sync[13]
rxhd[29]
rxhd[21]
rxhd[13]
hdlen[1]
chhd[5]
hden[5]
adc8[5]
sync[5]
rxhd[5]
pwst[0]
pksrch
agcen
fo[5]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
D5
Reserved
afc_corr[6]
peakdeten
enphpwdn
adrssia[4]
adrssib[4]
prealen[4]
Reserved
ookcnt[4]
Afclim[4]
preath[1]
chhd[28]
chhd[20]
chhd[12]
hden[28]
hden[20]
hden[12]
rxplen[4]
dtmod[0]
attack[0]
sync[28]
sync[20]
sync[12]
rxhd[28]
rxhd[20]
rxhd[12]
skip2ph
hdlen[0]
chhd[4]
hden[4]
adc8[4]
sync[4]
lnagain
rxhd[4]
clkhyst
pkrx
fo[4]
D4
Data
afc_corr[5]
prealen[3]
chfiladd[3]
adrssia[3]
adrssib[3]
Reserved
Reserved
ookcnt[3]
madeten
preath[0]
hden[27]
hden[19]
enbias2x
Afclim[3]
decay[3]
sync[27]
sync[19]
chhd[27]
chhd[19]
chhd[11]
hden[11]
rxplen[3]
manppol
sync[11]
rxhd[27]
rxhd[19]
rxhd[11]
fixpklen
hden[3]
sync[3]
chhd[3]
adc8[3]
pkvalid
rxhd[3]
eninv
pga3
fo[3]
D3
afc_corr[4]
ookcnt[10]
synclen[1]
chfiladd[2]
adrssia[2]
adrssib[2]
prealen[2]
rssi_off[2]
enmaninv
Reserved
ookcnt[2]
enamp2x
Afclim[2]
decay[2]
chhd[26]
chhd[18]
chhd[10]
hden[26]
hden[18]
hden[10]
rxplen[2]
crcerror
sync[26]
sync[18]
sync[10]
rxhd[26]
rxhd[18]
rxhd[10]
chhd[2]
hden[2]
adc8[2]
sync[2]
rxhd[2]
encrc
pga2
fd[8]
fo[2]
D2
hdch[3:0]
Si4330-B1
afc_corr[3]
synclen[0]
prealen[1]
chfiladd[1]
adrssia[1]
adrssib[1]
Reserved
rssi_off[1]
modtyp[1]
ookcnt[9]
ookcnt[1]
enmanch
hden[25]
hden[17]
Afclim[1]
decay[1]
sync[25]
sync[17]
chhd[25]
chhd[17]
rxplen[1]
rxhd[25]
rxhd[17]
hden[9]
hden[1]
sync[9]
sync[1]
chhd[9]
chhd[1]
adc8[1]
rxhd[9]
rxhd[1]
bufovr
crc[1]
pga1
fo[1]
fo[9]
D1
afc_corr[2]
prealen[0]
chfiladd[0]
adrssia[0]
adrssib[0]
Reserved
prealen[8]
rssi_off[0]
modtyp[0]
ookcnt[8]
ookcnt[0]
hden[24]
hden[16]
Afclim[0]
decay[0]
chhd[24]
chhd[16]
rxplen[0]
sync[24]
sync[16]
rxhd[24]
rxhd[16]
enwhite
chhd[8]
chhd[0]
hden[8]
hden[0]
adc8[0]
sync[8]
sync[0]
rxhd[8]
rxhd[0]
enbuf
crc[0]
pga0
fo[0]
fo[8]
D0
55
Default
POR
BCh
8Dh
0Ch
2Dh
D4h
0Ch
00h
18h
26h
22h
08h
2Ah
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
FFh
10h
00h
24h
20h
00h
00h
00h
00h
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