CYWUSB6935-48LFXC Cypress Semiconductor Corp, CYWUSB6935-48LFXC Datasheet - Page 11

• Manufacturer Part Number: CYWUSB6935-48LFXC
• Description: IC USB WIRELESS 2.4GHZ 48VQFN
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYWUSB6935-48LFXC

• Frequency: 2.4GHz
• Data Rate - Maximum: 62.5kbps
• Modulation Or Protocol: DSSS, GFSK
• Applications: AMR, ISM, RKE
• Power - Output: 0dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2.7 V ~ 3.6 V
• Current - Receiving: 57.7mA
• Current - Transmitting: 69.1mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Transmitting Current: 69.1mA
• Data Rate: 62.5Kbps
• Frequency Range: 2.4GHz To 2.483GHz
• Modulation Type: GFSK
• Rf Ic Case Style: QFN
• No. Of Pins: 48
• Supply Voltage Range: 2.7V To 3.6V
• Operating: RoHS Compliant
• Sensitivity Dbm: -95dBm
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1625

Document 38-16008 Rev. *A
Bit
7:2
1:0
Bit
7:4
3
2:0
Name
Reserved
IRQ Pin Select The Interrupt Request Pin Select bits are used to determine the drive method of the IRQ pin.
Reserved
EOF Length
Name
SERDES Enable The SERDES Enable bit is used to switch between bit-serial mode and SERDES mode.
7
7
Addr: 0x05
Addr: 0x06
Description
These bits are reserved and should be written with zeroes.
11 = Open Source (IRQ asserted = 1, IRQ deasserted = Hi-Z)
10 = Open Drain (IRQ asserted = 0, IRQ deasserted = Hi-Z)
01 = CMOS (IRQ asserted = 1, IRQ deasserted = 0)
00 = CMOS Inverted (IRQ asserted = 0, IRQ deasserted = 1)
Description
These bits are reserved and should be written with zeroes.
When the SERDES is enabled data can be written to and read from the IC one byte at a time, through the use of
the SERDES Data registers. The bit-serial mode requires bits to be written one bit at a time through the use of
the DIO/DIOVAL pins, refer to section 3.2. It is recommended that SERDES mode be used to avoid the need to
manage the timing required by the bit-serial mode.
The End of Frame Length bits are used to set the number of sequential bit times for an inter-frame gap without
valid data before an EOF event will be generated. When in receive mode and a valid bit has been received the
EOF event can then be identified by the number of bit times that expire without correlating any new data. The
EOF event causes data to be moved to the proper SERDES Data Register and can also be used to generate
interrupts. If 0 is the EOF length, an EOF condition will occur at the first invalid bit after a valid reception.
6
6
1 = SERDES enabled
0 = SERDES disabled, bit-serial mode enabled
Reserved
5
5
Reserved
Figure 7-7. SERDES Control
Figure 7-6. Configuration
REG_SERDES_CTL
4
4
REG_CONFIG
SERDES
Enable
3
3
2
2
EOF Length
1
1
CYWUSB6935
Default: 0x01
Default: 0x03
IRQ Pin Select
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