CYWUSB6935-48LFXC Cypress Semiconductor Corp, CYWUSB6935-48LFXC Datasheet - Page 18

• Manufacturer Part Number: CYWUSB6935-48LFXC
• Description: IC USB WIRELESS 2.4GHZ 48VQFN
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYWUSB6935-48LFXC

• Frequency: 2.4GHz
• Data Rate - Maximum: 62.5kbps
• Modulation Or Protocol: DSSS, GFSK
• Applications: AMR, ISM, RKE
• Power - Output: 0dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2.7 V ~ 3.6 V
• Current - Receiving: 57.7mA
• Current - Transmitting: 69.1mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Transmitting Current: 69.1mA
• Data Rate: 62.5Kbps
• Frequency Range: 2.4GHz To 2.483GHz
• Modulation Type: GFSK
• Rf Ic Case Style: QFN
• No. Of Pins: 48
• Supply Voltage Range: 2.7V To 3.6V
• Operating: RoHS Compliant
• Sensitivity Dbm: -95dBm
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1625

Document 38-16008 Rev. *A
Bit
7:1
0
Bit
7:1
0
Bit
7
6
5
4:3
2
1
0
Reserved
Name
Reserved
Wakeup Enable Wakeup interrupt enable.
Name
Reserved
Reg Write Control Enables write access to Reg 0x2E and Reg 0x2F.
MID Read Enable The MID Read Enable bit must be set to read the contents of the Manufacturing ID register (Reg 0x3C-0x3F).
Reserved
PA Output Enable The Power Amplifier Output Enable bit is used to enable the PACTL pin for control of an external power amplifier.
PA Invert
Reset
Name
Reserved
Wakeup Status
7
7
7
Addr: 0x1C
Addr: 0x1D
Addr: 0x20
Reg Write
Control
Description
These bits are reserved and should be written with zeroes.
0 = disabled
1 = enabled
A wakeup event is triggered when the PD pin is deasserted and once the IC is ready to receive SPI communications.
Description
These bits are reserved. This register is read-only.
Wakeup status.
0 = Wake interrupt not pending
1 = Wake interrupt pending
This IRQ will assert when a wakeup condition occurs. This bit is cleared by reading the Wake Status register (Reg
0x1D). This register is read-only.
6
6
6
Description
This bit is reserved and should be written with zero.
These bits are reserved and should be written with zeroes.
The Power Amplifier Invert bit is used to specify the polarity of the PACTL signal when the PaOe bit is set high.
PA Output Enable and PA Invert cannot be simultaneously changed.
The Reset bit is used to generate a self-clearing device reset.
Enabling the Manufacturing ID register (Reg 0x3C-0x3F) consumes power. This bit should only be set when
reading the contents of the Manufacturing ID register (Reg 0x3C-0x3F).
1 = Enables write access to Reg 0x2E and Reg 0x2F
1 = Enables read of MID registers
0 = Reg 0x2E and Reg 0x2F are read-only
0 = Disables read of MID registers
1 = PA Control Output Enabled on PACTL pin
0 = PA Control Output Disabled on PACTL pin
1 = PACTL active low
0 = PACTL active high
1 = Device Reset. All registers are restored to their default values.
0 = No Device Reset.
MID Read
Enable
5
5
5
Figure 7-23. Analog Control
Figure 7-21. Wake Enable
Figure 7-22. Wake Status
Reserved
Reserved
Reserved
REG_ANALOG_CTL
REG_WAKE_STAT
REG_WAKE_EN
4
4
4
Reserved
3
3
3
PA Output
Enable
2
2
2
PA Invert
1
1
1
CYWUSB6935
Default: 0x01
Default: 0x00
Default: 0x00
Wakeup Enable
Wakeup Status
Page 18 of 32
Reset
0
0
0