ATSAM3N4AA-MU Atmel, ATSAM3N4AA-MU Datasheet - Page 24

• Manufacturer Part Number: ATSAM3N4AA-MU
• Description: MCU FLASH 48-QFN
• Manufacturer: Atmel
• Series: SAM3Nr

Specifications of ATSAM3N4AA-MU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: SAM3N
• Core: ARM Cortex M3
• Data Bus Width: 10 bit
• Interface Type: SPI, UART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 79
• Operating Supply Voltage: 1.62 V to 3.6 V
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Table 6-1.
Notes:
6.2.1
24
SYSTEM_IO
bit number
1. If PB12 is used as PIO input in user applications, a low level must be ensured at startup to prevent Flash erase before the
2. In the product Datasheet Refer to: Slow Clock Generator of the Supply Controller section.
3. In the product Datasheet Refer to: 3 to 20 MHZ Crystal Oscillator information in the PMC section.
12
SAM3N Summary
7
6
5
4
-
-
-
-
Serial Wire JTAG Debug Port (SWJ-DP) Pins
user application sets PB12 into PIO mode.
System I/O Configuration Pin List.
TDO/TRACESWO
Default function
TCK/SWCLK
The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/SWO, TDI and commonly provided on
a standard 20-pin JTAG connector defined by ARM. For more details about voltage reference
and reset state, refer to
At startup, SWJ-DP pins are configured in SWJ-DP mode to allow connection with debugging
probe. Please refer to the Debug and Test Section of the product datasheet.
SWJ-DP pins can be used as standard I/Os to provide users more general input/output pins
when the debug port is not needed in the end application. Mode selection between SWJ-DP
mode (System IO mode) and general IO mode is performed through the AHB Matrix Special
Function Registers (MATRIX_SFR). Configuration of the pad for pull-up, triggers, debouncing
and glitch filters is possible regardless of the mode.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It
integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left uncon-
nected for normal operations.
By default, the JTAG Debug Port is active. If the debugger host wants to switch to the Serial
Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and
TCK/SWCLK which disables the JTAG-DP and enables the SW-DP. When the Serial Wire
Debug Port is active, TDO/TRACESWO can be used for trace.
The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous
trace can only be used with SW-DP, not JTAG-DP. For more information about SW-DP and
JTAG-DP switching, please refer to the Debug and Test Section.
TMS/SWDIO
after reset
ERASE
PB9
PB8
PA7
PA8
TDI
Other function
XOUT32
Table 3-1 on page
PB12
XIN32
XOUT
PB7
PB6
PB5
PB4
XIN
Constraints for
6.
normal start
Low Level at
startup
-
-
-
-
-
-
-
-
(1)
In Matrix User Interface Registers
Configuration Register in the Bus
Matrix section of the product
(Refer to the System I/O
See footnote
See footnote
Configuration
datasheet.)
11011AS–ATARM–04-Oct-10
(2)
(3)
below
below