ATSAM3N4AA-MU Atmel, ATSAM3N4AA-MU Datasheet - Page 32

• Manufacturer Part Number: ATSAM3N4AA-MU
• Description: MCU FLASH 48-QFN
• Manufacturer: Atmel
• Series: SAM3Nr

Specifications of ATSAM3N4AA-MU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: SAM3N
• Core: ARM Cortex M3
• Data Bus Width: 10 bit
• Interface Type: SPI, UART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 79
• Operating Supply Voltage: 1.62 V to 3.6 V
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

8.2.3.9
8.2.3.10
8.2.3.11
8.2.4
32
SAM3N Summary
Boot Strategies
Fast Flash Programming Interface
SAM-BA Boot
GPNVM Bits
The Fast Flash Programming Interface allows programming the device through either a serial
JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang program-
ming with market-standard industrial programmers.
The FFPI supports read, page program, page erase, full erase, lock, unlock and protect
commands.
The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered
when TST and PA0 and PA1are tied low.
The SAM-BA Boot is a default Boot Program which provides an easy way to program in-situ the
on-chip Flash memory.
The SAM-BA Boot Assistant supports serial communication via the UART0.
The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).
The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is set to 0.
The SAM3N features three GPNVM bits that can be cleared or set respectively through the com-
mands “Clear GPNVM Bit” and “Set GPNVM Bit” of the EEFC User Interface.
.
Table 8-2.
The system always boots at address 0x0. To ensure a maximum boot possibilities the memory
layout can be changed via GPNVM.
A general purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the
Flash.
The GPNVM bit can be cleared or set respectively through the commands “Clear General-pur-
pose NVM Bit” and “Set General-purpose NVM Bit” of the EEFC User Interface.
Setting the GPNVM Bit 1 selects the boot from the Flash, clearing it selects the boot from the
ROM. Asserting ERASE clears the GPNVM Bit 1 and thus selects the boot from the ROM by
default.
GPNVMBit[#]
0
1
General-purpose Non volatile Memory Bits
Boot mode selection
Security bit
Function
11011AS–ATARM–04-Oct-10