ATSAM3N4AA-MU Atmel, ATSAM3N4AA-MU Datasheet - Page 27

MCU FLASH 48-QFN

ATSAM3N4AA-MU

Manufacturer Part Number
ATSAM3N4AA-MU
Description
MCU FLASH 48-QFN
Manufacturer
Atmel
Series
SAM3Nr
Datasheet

Specifications of ATSAM3N4AA-MU

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
48MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
SAM3N
Core
ARM Cortex M3
Data Bus Width
10 bit
Interface Type
SPI, UART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
79
Operating Supply Voltage
1.62 V to 3.6 V
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
7.5
7.6
11011AS–ATARM–04-Oct-10
Master to Slave Access
Peripheral DMA Controller
All the Masters can normally access all the Slaves. However, some paths do not make sense,
for example allowing access from the Cortex-M3 S Bus to the Internal ROM. Thus, these paths
are forbidden or simply not wired, and shown as “-” in
Table 7-3.
The Peripheral DMA Controller handles transfer requests from the channel according to the fol-
lowing priorities (Low to High priorities):
Table 7-4.
Instance name
• Handles data transfer between peripherals and memories
• Low bus arbitration overhead
• Next Pointer management for reducing interrupt latency requirement
0
1
2
3
USART0
USART0
UART0
UART0
– One Master Clock cycle needed for a transfer from memory to peripheral
– Two Master Clock cycles needed for a transfer from peripheral to memory
TWI0
TWI0
ADC
DAC
SPI
SPI
SAM3N Master to Slave Access
Peripheral DMA Controller
Peripheral Bridge
Internal SRAM
Internal Flash
Internal ROM
Channel T/R
Masters
Slaves
Transmit
Transmit
Transmit
Transmit
Transmit
Receive
Receive
Receive
Receive
Receive
100 & 64 Pins
Cortex-M3 I/D Bus
x
x
x
x
x
x
x
x
x
x
Table
X
X
0
-
-
7-3.
48 Pins
SAM3N Summary
N/A
x
x
x
x
x
x
x
x
x
Cortex-M3 S Bus
X
X
1
-
-
PDC
X
X
X
2
-
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