ATSAM3N4AA-MU Atmel, ATSAM3N4AA-MU Datasheet - Page 37

• Manufacturer Part Number: ATSAM3N4AA-MU
• Description: MCU FLASH 48-QFN
• Manufacturer: Atmel
• Series: SAM3Nr

Specifications of ATSAM3N4AA-MU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: SAM3N
• Core: ARM Cortex M3
• Data Bus Width: 10 bit
• Interface Type: SPI, UART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 79
• Operating Supply Voltage: 1.62 V to 3.6 V
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

9.6
9.7
11011AS–ATARM–04-Oct-10
Power Management Controller
Watchdog Timer
The Power Management Controller provides all the clock signals to the system. It provides:
The Supply Controller selects between the 32 kHz RC oscillator or the crystal oscillator. The
unused oscillator is disabled automatically so that power consumption is optimized.
By default, at startup the chip runs out of the Master Clock using the Fast RC Oscillator running
at 4 MHz.
The user can trim by software the 8 and 12 MHz RC Oscillator frequency.
Figure 9-3.
The SysTick calibration value is fixed at 6000 which allows the generation of a time base of 1 ms
with SysTick clock at 6 MHz (48 MHz/8)
• the Processor Clock HCLK
• the Free running processor clock FCLK
• the Cortex SysTick external clock
• the Master Clock MCK, in particular to the Matrix and the memory interfaces
• independent peripheral clocks, typically at the frequency of MCK
• three programmable clock outputs: PCK0, PCK1 and PCK2
• 16-bit key-protected only-once-Programmable Counter
• Windowed, prevents the processor to be in a dead-lock on the watchdog access
MAINCK
PLLCK
SAM3N4/2/1 Power Management Controller Block Diagram
SLCK
Master Clock Controller
MAINCK
PLLCK
SLCK
/1,/2,/4,..,/64
Prescaler
Programmable Clock Controller
/1,/2,/4,..,/64
Prescaler
Sleep Mode
Clock Controller
Processor
Controller
ON/OFF
Divider
Clock
Peripherals
ON/OFF
/8
SAM3N Summary
HCK
int
SystTick
FCLK
MCK
periph_clk[..]
pck[..]
37