MC9S08JE64CLH Freescale Semiconductor, MC9S08JE64CLH Datasheet - Page 24

IC MCU 8BIT 64K FLASH 64LQFP

MC9S08JE64CLH

Manufacturer Part Number
MC9S08JE64CLH
Description
IC MCU 8BIT 64K FLASH 64LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet

Specifications of MC9S08JE64CLH

Core Processor
HCS08
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SCI, SPI, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 6x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
S08JE
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
12 KB
Maximum Clock Frequency
48 MHz
Operating Supply Voltage
- 0.3 V to + 3.8 V
Maximum Operating Temperature
+ 105 C
3rd Party Development Tools
EWS08
Development Tools By Supplier
TWR-SER, TWR-ELEV, TWR-MCF51JE-KIT, TWR-S08JE128-KIT, TWR-LCD
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S08JE64CLH
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Preliminary Electrical Characteristics
24
10
11
12
13
14
15
16
#
1
2
3
4
5
6
7
8
9
Resolution
Supply current low-power mode
Supply current high-power mode
Full-scale Settling time
(±0.5 LSB)
(0x080 to 0xF7F or 0xF7F to 0x080)
low-power mode
Full-scale Settling time
(±0.5 LSB)
(0x080 to 0xF7F or 0xF7F to 0x080)
high-power mode
Code-to-code Settling time
(±0.5 LSB)
(0xBF8 to 0xC08 or 0xC08 to
0xBF8)
low-power mode
Code-to-code Settling time
(±0.5 LSB)
(0xBF8 to 0xC08 or 0xC08 to
0xBF8)
high-power mode
DAC output voltage range low
(high-power mode, no load, DAC
set to 0)
DAC output voltage range high
(high-power mode, no load, DAC
set to 0x0FFF)
Integral non-linearity error
Differential non-linearity error
VDACR is > 2.4 V
Offset error
Gain error
Power supply rejection ratio
V
Temperature drift of offset voltage
(DAC set to 0x0800)
Offset aging coefficient
DD
≥ 2.4 V
Characteristic
Figure 5. Offset at Half Scale vs Temperature
Table 14. DAC 12-Bit Operating Behaviors
Preliminary — Subject to Change
I
I
DDA_DACHP
DDA_DACLP
Ts
Ts
Symbol
Ts
V
Ts
V
PSRR
dacouth
DNL
dacoutl
C-C
C-C
INL
T
FS
E
E
FS
A
N
co
O
G
c
HP
LP
HP
LP
12
50
120
V
100
60
Min
DACR
-
12
100
500
(TBD)
200
(TBD)
30
5
1(TBD)
100
(TBD)
± 8
± 1
± 0.5
± 0.5
(TBD)
2
(TBD)
TBD
Max
bit
µA
µA
µs
µs
µs
µs
mV
mV
LSB
LSB
%FSR
%FSR
dB
mV
µV/yr
Unit
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
Freescale Semiconductor
See Typical
Drift figure that
follows.
Notes

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