PK60N512VMD100 Freescale Semiconductor, PK60N512VMD100 Datasheet - Page 24

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PK60N512VMD100

Manufacturer Part Number
PK60N512VMD100
Description
IC ARM CORTEX MCU 512K 144-MAP
Manufacturer
Freescale Semiconductor
Series
Kinetisr
Datasheets

Specifications of PK60N512VMD100

Core Processor
ARM Cortex-M4
Core Size
32-Bit
Speed
100MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, IrDA, SDHC, SPI, UART/USART, USB, USB OTG
Peripherals
DMA, I²S, LVD, POR, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.71 V ~ 3.6 V
Data Converters
A/D 33x16b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LBGA
Processor Series
Kinetis
Core
ARM Cortex M4
Data Ram Size
128 KB
Interface Type
UART, SPI, I2C, I2S, CAN
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
100
Operating Supply Voltage
1.71 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PK60N512VMD100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
PK60N512VMD100
Manufacturer:
FREESCALE
Quantity:
20 000
Peripheral operating requirements and behaviors
24
Symbol
J10
J11
J12
J13
J14
J3
J4
J5
J6
J7
J8
J9
TCLK (input)
TCLK clock pulse width
TCLK rise and fall times
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
Description
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
Table 12. JTAG full voltage range electricals (continued)
K60 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Figure 5. Test clock input timing
J4
Preliminary
J3
J2
J4
J3
12.5
Min.
100
1.4
50
25
20
0
8
8
Freescale Semiconductor, Inc.
Max.
22.1
22.1
25
25
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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