L6460 STMicroelectronics, L6460 Datasheet

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... PWM generators – 14 GPIOs Description The L6460 is optimized to control and drive multi- motor system providing a unique level of integration in term of control, power and auxiliary features. Thanks to the high configurability L6460 can be customized to drive different motor ...

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... Contents Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 L6460’s main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 Operating ratings specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 Internal supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.1 V SupplyInt 4.2 Charge pump regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.3 V3v3 regulator ...

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... L6460 8.6.1 8.6.2 8.6.3 8.6.4 8.6.5 8.6.6 9 Power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.1 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.2 Hibernate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.3 Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.4 nAWAKE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11 Linear main regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12 Main switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.1 Pulse skipping operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13 Switching regulator controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13 ...

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... GPIO[ 111 22.8 GPIO[ 113 22.9 GPIO[ 115 22.10 GPIO[ 117 22.11 GPIO[10 119 22.12 GPIO[11 121 22.13 GPIO[12 123 22.14 GPIO[13 125 22.15 GPIO[14 127 23 Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 23.1 Read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 23.2 Write transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 4/139 Doc ID 17713 Rev 1 L6460 ...

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... L6460 24 Registers list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 25 Schematic examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 26 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Doc ID 17713 Rev 1 Contents 5/139 ...

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... GPIO[1] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 43. GPIO[2] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 44. GPIO[3] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 45. GPIO[4] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 46. GPIO[5] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 47. GPIO[6] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 48. GPIO[7] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Table 49. GPIO[8] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6/139 Doc ID 17713 Rev 1 L6460 ...

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... L6460 Table 50. GPIO[9] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 51. GPIO[10] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 52. GPIO[11] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 53. GPIO[12] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Table 54. GPIO[13] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table 55. GPIO[14] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 56. Register address map 132 Table 57. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 ...

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... GPIO[5] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 36. GPIO[6] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Figure 37. GPIO[7] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Figure 38. GPIO[8] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Figure 39. GPIO[9] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Figure 40. GPIO[10] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Figure 41. GPIO[11] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Figure 42. GPIO[12] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 8/139 Doc ID 17713 Rev 1 L6460 ...

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... L6460 Figure 43. GPIO[13] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Figure 44. GPIO[14] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Figure 45. SPI read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Figure 46. SPI write transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Figure 47. SPI input timing diagram 131 Figure 48. SPI output timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Figure 49. Application with 2 DC motors, 1 stepper motor and 3 power supplies . . . . . . . . . . . . . . . 135 Figure 50 ...

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... General description 1.1 Overview L6460 offers the possibility to control and power multi motor systems, through the management of simultaneous driving of stepper and DC motor. A number of features can be configured through the digital interface (SPI), including 3 voltage regulators, 1 high precision A/D converter, 2 operational amplifiers and 14 configurable GPIOs. ...

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... L6460 1.2 Pin connection Figure 2. Pin connection DC1_PLUS V SWDRV_SNS V SWDRV_FB GPIO4 GPIO3 DC1_MINUS DC1_MINUS GND1 GND2 DC2_MINUS 10 DC2_MINUS 11 GPIO2 12 GPIO1 13 GPIO0 14 nSS 15 DC2_PLUS GND_PAD Doc ID 17713 Rev 1 General description DC3_SENSE 47 GPIO5 46 GPIO9 45 GPIO10 44 GPIO11 43 N.C. 42 DC3_MINUS 41 DC3_SENSE 40 DC4_SENSE 39 DC4_MINUS 38 N.C. 37 GPIO14 ...

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... Regulator voltage feedback Regulator current feedback SPI input clock pin Main voltage supply Bridge 4 phase “plus” output Not connected (4) Device wake up Doc ID 17713 Rev 1 L6460 Type Output Analog input Analog input Analog In/Out - CMOS bi-dir Analog In/Out - CMOS bi-dir Output Output ...

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... L6460 Table 2. Pins configuration (continued) Pin # Pin name 35 GPIO12 36 GPIO13 37 GPIO14 38 N.C. 39 DC4_MINUS Bridge 4 phase “minus” output 40 DC4_SENSE Bridge 4 sense output 41 DC3_SENSE Bridge 3 sense output 42 DC3_MINUS Bridge 3 phase “minus” output 43 N.C. 44 GPIO11 45 GPIO10 46 GPIO9 47 GPIO5 48 DC3_SENSE Bridge 3 sense output 49 N ...

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... L6460’s main features 2 L6460’s main features L6460 includes the following circuits: ● Four widely configurable full bridges: – Bridges 1 and 2: – Diagonal R – Max operative current = 2.5 A. – Bridges 3 and 4: – Diagonal R – Max operative current = 1.5 A. ● Possible configurations for each bridge are the following: – ...

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... Very low power dissipation in “low power mode” (~35 mW) L6460 is intended to maximize the use of its components, so when an internal circuit is not used it could be employed for other applications. Bridge 3, for example, can be used as a full bridge or to implement two switching regulators with synchronous rectification: to obtain this flexibility L6460 includes 2 separate regulation loops for these regulators ...

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... Electrical specifications 3.1 Absolute maximum rating The following specifications define the maximum range of voltages or currents for L6460. Stresses above these absolute maximum specifications may cause permanent damage to the device. Exposure to absolute maximum ratings for extended periods may affect device reliability. Table 3. ...

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... L6460 Table 4. IC operating ratings Parameter V Gate drive pin voltage SWDRV_GATE V Sense pin voltage SWDRV_SNS T Junction temperature J 1. For V lower than external resistor between V supply For V lower than 15 V external diodes for charge pump are required. supply 2. Operating supply current is measured with system regulators operating but not loaded. ...

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... Watchdog clock period clk Internal clock F Oscillator frequency osc nAWAKE function nAWAKE low logic level V IL voltage 18/139 Test condition I=1mA (3) C=50pF ( 3.3 V 3V3 Doc ID 17713 Rev 1 L6460 Min Typ Max Unit 15 ns 150 ns 10.2 11 11.8 V 10.5 11.5 12.5 V 0.3 0.5 0.7 V 3.5 µ ...

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... L6460 Table 5. Electrical characteristics (continued) Parameter Description nAWAKE high logic level V IH voltage V nAWAKE input hysteresis HYS I nAWAKE pin output current OUT I nAWAKE pin input current INP t Filter time AWAKEFILT Main linear regulator V Drop out voltage drop Internal switch pull down ...

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... Supply T = 125°C junction V = 36V, Supply T = 125°C junction (8) SelFBref = ‘00’ SelFBref = ‘01’ SelFBref = ‘10’ SelFBref = ‘11’ 36V, Supply T = 125°C junction Doc ID 17713 Rev 1 L6460 Min Typ Max Unit ±3% 84.5 87 89.5 % 90 µs 3 2.3 3 ...

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... L6460 Table 5. Electrical characteristics (continued) Parameter Description V Under voltage falling threshold SWD_UV_f V Under voltage rising threshold SWD_UV_r V Under voltage hysteresis SWD_UV_hys t Under voltage deglitch filter prim_uv V Over current threshold voltage ovc t Current limit deglitch time deglitch t Current limit response time I_lim ...

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... SelStepRef =1 (8) StepBlkTime = ‘00’ StepBlkTime = ‘01’ StepBlkTime = ‘10’ StepBlkTime = ‘11’ (26 125°C junction V = 36V Supply T = 125°C junction Doc ID 17713 Rev 1 L6460 Min Typ Max Unit μ µs 120 µs 240 µs 480 µs 100 180 250 ...

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... L6460 Table 5. Electrical characteristics (continued) Parameter Description Synchronous buck regulator V FBREF feedback reference voltage I GPIO feedback pin current GPIO_FB V Output voltage range out I Output load current load R Internal high/low side R DSonHS V Loop voltage accuracy loop V Under voltage falling threshold REG_UV_f V Under voltage rising threshold ...

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... R LOAD A2dType = 0 (30)(31) A2dType = 0 (32)(31) A2dType = 0 (33) A2dType = 0 A2dType = 0 over time and temperature (34) A2dType = 0 A2dType = 0 over time and temperature (35) Doc ID 17713 Rev 1 L6460 Min Typ Max Unit 0.873 0.9 0.927 V 1.394 1.437 1.48 V 1.746 1.8 1.854 V 2.182 2.25 2 ...

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... L6460 Table 5. Electrical characteristics (continued) Parameter Description C Input sampling capacitance in (37) ADC with A2DType=1 IMR Measurement range INL Integral non-linearity DNL Differential Non-Linearity OE Offset error OE Offset error drift Drift GE Gain error GE Gain error drift Drift t Minimum conversion time conv Resolution C Input sampling capacitance ...

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... ICM 2 GPIO_SPI 12 20 1.3 1.75 0.3 0.6 (42)(43) 0.15 (42)(43) 0.25 (42)(43) 0.2 (42)(43) 2.4 0.6 150 250 50 L6460 Max Unit 1.03 1.7 V 2.06 2.575 150 nA 500 MHz V/µs 2 µs 0.4 µs 0.5 µs 0.4 µs 3 ...

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... L6460 Table 5. Electrical characteristics (continued) Parameter Description t Current limit response time I_lim C Max load capacitance LOAD t Turn on propagation delay ON t Turn off propagation delay OFF Interrupt controller t Pulse duration PULSE t Filter time INTFILT GPIO[0], GPIO[1], GPIO[2], GPIO[3], GPIO[4], GPIO[6] V High level input voltage ...

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... MOSI maximum load LOAD 1. This value is useful to define the voltage rating for external capacitor to be connected from V 2. This typical value is only intended to give an estimation of the current consumption when L6460 is configured in simple regulators mode (see following Chapter typical value allows a raw choose of the external resistor but the definitive choose must be done according to the ...

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... L6460 10. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (V 11. This condition is intended to simulate an extra current on output. 12. This condition is intended to simulate a short circuit on output. 13. Rise and fall time are measured between 10% and 90% V 14. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (V 15 ...

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... Internal supplies 4 Internal supplies L6460 includes three internal regulators used to provide a regulated voltage to internal circuits. The internal regulators are the following regulator. SupplyInt - Charge pump regulator regulator. 3v3 4.1 V regulator SupplyInt V is the output of an internal regulator used to supply some internal circuits. This ...

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... V voltage reaches its undervoltage rising threshold Pump below its under voltage falling threshold, all the regulators will be switched off. The charge pump circuit is disabled when L6460 is in “low power mode”. Figure 4. Charge pump block diagram EnVPump An example of capacitors value is: 4 ...

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... V threshold. When POR output signal is active, all functions and all flags inside L6460 are set in their reset state; once POR signal comes back from off state (meaning monitored voltages are above their rising threshold), the power up sequence is re-initialized. ...

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... When nRST_int becomes active (logic level = “0”) it sets in their reset state some of the functions inside L6460. The main functions that will be reset by nRST_int signal are the following: – Serial interface will be reset and will not accept any other command. ...

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... All regulator voltages included in power up sequence (V considered as nRESET circuit voltages. 34/139 t nRST_int V UV Supply UV Filter V UV SupplyInt UV Filter V UV Pump UV Filter UV Filter regulators System UV UV Filter to SPI Doc ID 17713 Rev 1 L6460 Filter nRESET nRESET pin Driver nGateCtrl POR – Figure 5) will be SysX SysY pin ...

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... Warm temperature. At this point, L6460 will restart the power up sequence and TSD bit will be set and will be readable as soon as L6460 will come out from the reset state. ...

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... Watchdog circuit The Watchdog timer can be used to reset L6460 not serviced by the firmware that can periodically write at logic level “1’ the ClrWDog bit in the WatchDogStatus register. This circuit is disabled by default; firmware can enable it by setting at logic level ‘1’ the WDEnable bit in the WatchDogCfg register. When the Watchdog timeout event happens, L6460 sets to ‘ ...

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... L6460 Table 7. Watchdog timeout specifications WDdelay[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Doc ID 17713 Rev 1 Watchdog circuit WD timeout Typ 8*WD_Tclk 9*WD_Tclk 10*WD_Tclk 11*WD_Tclk 12*WD_Tclk 13*WD_Tclk 14*WD_Tclk 15*WD_Tclk 16*WD_Tclk 17*WD_Tclk 18*WD_Tclk 19*WD_Tclk ...

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... Internal clock oscillator 7 Internal clock oscillator L6460 includes a free running oscillator that does not require any external components. This circuit is used to generate the time base needed to generate the internal timings; the typical frequency is 16 MHz. The oscillator circuit starts as soon as the IC exits from the power on reset condition and it is stopped only when in “ ...

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... When it reaches its final value, L6460 enables the GPIO[0] pin state read circuitry, and, after a time TpinSample, it will sample the GPIO[0] state found high impedance, L6460 does not consider GPIO[3] and GPIO[4] pins state and starts its “Basic device” mode sequence. If GPIO[0] is found to be connected to ground or to V3v3, L6460 checks the state of GPIO[3] and GPIO[4] pins to select its start-up configuration ...

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... Basic device mode The basic device mode is selected by leaving the GPIO[0] pin floating. In this mode L6460 doesn’t use GPIO[3] and GPIO[4] as configuration pins, leaving them free for other uses. When in this mode the regulators included in the start up sequence (except V considered as system regulators and they start in the following sequence: 1 ...

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... Slave device mode In slave device mode, L6460 consider the nAWAKE pin as an input enable. Since this is now a digital pin, the current pull up source inside the nAWAKE circuit is disabled. At the startup, if the nAWAKE pin is found to be low for a period higher than t L6460 enters directly in the “ ...

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... Switching regulator controller regulator (V 3. Main linear regulator (V 42/139 ). AUX1_SW ) together with main linear regulator (V SWmain ) (Not system regulator). AUX2_SW ). SWmain ) AUX1_SW ) AUX2_SW ). AUX1_SW ) AUX2_SW ) LINmain ) (not system regulator). SWmain mode ) is included in start-up. SWDRV ). SWmain SWDRV ). LINmain Doc ID 17713 Rev 1 LINmain ). L6460 ). ...

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... L6460 8.6.6 Secondary regulators mode In this configuration, bridge 3 is configured as a single synchronous switching regulator using its two half bridges in parallel (V When in this mode the power-up sequence is: 1. Main switching regulator (V 2. Auxiliary switching regulator (V 3. Main linear regulator (V ). AUX_(1//2)SW ) ...

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... L6460 enters in the normal operating state, that will release nRESET pin and will wait for SPI commands. L6460 will reduce the noise introduced in the system by switching out of phase all its power circuits (switching regulators, bridges and charge pump). ...

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... To achieve this result there is the need to switch off the internal V use an additional pin to provide a 3.3 V supply to internal circuits. L6460 can do this by using the low voltage switch implemented on GPIO6 pin. This switch internally connects V ...

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... The exiting from hibernate mode is achieved by forcing at low level nAWAKE pin (or GPIO5 pin if L6460 is in Slave mode); L6460 will also exit from hibernate mode if an undervoltage event happens on V When the exit from hibernate mode is due to an external command, L6460 sets to ‘1’ the bit HibModeLth in the HibernateStatus register. 10.3 Low power mode When in normal operating mode, the microcontroller can place L6460 in “ ...

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... Here below is reported the nAWAKE pin simplified schematic. Figure 8. nAWAKE function block diagram SlaveMode AWAKE nAWAKE seen high for the first time after start up. will be disabled. If L6460 is configured as a Slave device, the INP and I will be disabled and the nAWAKE pin can be considered INP OUT AWAKE_req Doc ID 17713 Rev 1 ...

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... The linear main regulator is directly powered by V regulators that L6460 could consider as a system regulator. This means that the voltage generated by this regulator is not used to power any internal circuit, but L6460 will check that the feedback voltage V internal functions. When an under-voltage event (with a duration longer than period t ...

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... L6460 Figure 10. Linear main regulator with external bipolar for high current V Whichever configuration is used (regulator or controller), a ceramic capacitor must be connected on the output pin towards ground to guarantee the stability of the regulator; the value of this capacitance is in the range of 100 µF depending on the regulated voltage ...

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... It implements a soft start strategy and could be a system regulator so even if its output voltage V L6460 will check that the good value range before enabling all its internal functions. When L6460 detects a system regulator under-voltage event with a duration longer than the ...

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... L6460 Figure 11. Main switching regulator functional blocks Control From Central Logic Logic Under voltage flag To Central Logic In pulse skipping control the duty cycle must be chosen by the user depending on supply voltage and output regulated voltage. Therefore the switching regulator has 4 possible duty ...

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... The feedback reference voltage is selected by writing the SelFBRef bits in the SwCtrCfg. This regulator is switched off when L6460 is powered up for the first time and can be enabled using L6460’s SPI interface. Here after are summarized the main features of the regulator: – ...

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... L6460 Figure 12. Switching regulator controller functional blocks Charge pump Voltage Driver Control From Central Logic Logic SelFBRef [ 1:0] Regulator Freq Vref = 3 V VFBRef Vref = 3V Vref=0.8V Vref=0.8V under voltage flag Filter To Central Logic SelFBRef Uv Threshold 1 Uv Threshold 2 13.1 Pulse skipping operation Pulse skipping strategy has already been explained on main switching regulator section. ...

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... Figure 13: VPUMP I SOURCE Tsink I SINK and it is discharged towards ground with a current generator I pulse while an equivalent resistor R Table 13. < 5V out ≤ 32V out Doc ID 17713 Rev 1 V SWDRV_gate R SUSTAIN V SWDRV_SW SINK is connected between gate SUSTAIN Feedback voltage reference 0. 2. L6460 that is ...

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... L6460 An example of application can be considered the following, supposing the external mosfet type STD12NF06L: – Max DC current load = 3 A – Typ Over current threshold = 1.5 = 4.5 A – 150 µH – 220-330 µF In this conditions the step-down regulator will result over-load protected, short-circuit protected over all the regulated voltage range and the V Other application configurations could be evaluated before being implemented ...

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... Power bridges 14 Power bridges L6460 includes four H bridge power outputs (each one made by two independent half bridges) that are configurable in several different configurations. Each half bridge is protected against: over-current, over-temperature and short circuit to ground, to supply or across the load. When an over current event occurs, all outputs are turned off (after a filter time), and the over current bit is stored in the internal status register that can be read through SPI ...

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... In Figure 15 is reported a block diagram representing the possible PWM choices for each L6460 half bridges. The figure is related only to bridges 1 and 2, but it could be assumed to be valid also for bridges 3 and 4, with few differences due to different possible configurations of these last drivers. MotorXPWM (Configurable by means of MtrXCfg ...

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... Motor2 PWM 01Aux2Pwm 10ExtPwm1 11ExtPwm2 Mtr2SelPWMSide B [1:0] 00 Motor2 PWM 01 Aux2Pwm 10 ExtPwm1 11 ExtPwm2 58/139 Motor 1 side A Logic Table Mtr1_2Parallel Mtr1Tablel[1:0] Motor 1 sideB Logic Table Bridge1 Mtr1_2Parallel Mtr2Tablel[1:0] Motor 2 side A Logic Table Mtr1_2Parallel Mtr2Tablel[1:0] Motor 2 sideB Logic Table Bridge 2 Doc ID 17713 Rev 1 L6460 ...

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... L6460 14.1 Possible configurations The selection of the bridge configuration is done through SPI, by writing the MtrXTable[1:0] bits in the MtrXCfg register. The table below shows the correspondence between MtrXTable[1:0] bits and the bridge configuration. Table 16. Bridge selection MtrXTable[ Bridge 1 & 2 can be paralleled by means of Mtr1_2Parallel bit in the Mtr1_2Cfg register: Bridge 1 and 2 paralleled will form superbridge1, bridge X side A and bridge X side B paralleled form SuperHalfBridgeX or SuperSwitchX ...

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... When a current limit event occurs this event will be latched and the bridges will remain in high impedance state for the off time. 60/139 Low Current MtrXCtrl power Enable limit SideA mode Doc ID 17713 Rev 1 MtrXCtrl PWM OUT+ SideB L6460 OUT ...

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... L6460 14.1.2 Parallel configuration (super bridge) Bridges and 4 can be configured to be used two by two (1 plus 2, 3 plus 4) as one super bridge thus enabling the driving of loads (motors) requiring high currents. In this configuration the half bridges will be paralleled and will work as one phase of the super- bridge just created: the two phases + will become phase + of the newly created super- bridge while the two phases - will become phase – ...

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... When a current limit event occurs this event will be latched and the bridges will remain in high impedance state for the off time. 62/139 V Supply V pump High side Driver Control Logic Low side Driver Low Current power Enable limit mode Doc ID 17713 Rev 1 L6460 DCX Phase output MtrXCtrl PWM OUT SideA ...

Page 63

... L6460 14.1.4 Switch configuration Each bridge can be configured to be used as 2 independent switches that connects the output to supply or to ground also possible to parallel the two switches and use them as a single super switch. All resulting switches will behave according to the following truth table. ...

Page 64

... Control type (external firmware control, half step, normal drive, wave drive, micro-step). ● current levels (quasi-sinusoidal increments) for each bridge. ● Current direction. ● Decay mode. ● Blanking time. ● Off time (32 values from 2µs to 64µs). ● Percentage of fast decay respect to toff (when in mixed decay mode). 64/139 Doc ID 17713 Rev 1 L6460 ...

Page 65

... Ref1 Ref2 SelStepRef Using the StepCtrlMode[2:0] bits in StepCfg1 register, L6460 can be programmed to internally generate the stepping levels. In these cases and depending on the StepFromGpio bit in the StpCfg1 register the Stepper driver will move to next step each time the StepCmd bit is set at logic level “1” each pulse transition longer than ~1µs externally applied on ...

Page 66

... Stepping sequence control left to the external No Control controller Half Step Half step Normal Step Full step (two phases on) Wave Drive Full step (one phase on) 1/4 Step Four micro steps 1/8 Step Eight micro steps 1/16 Step Sixteen micro steps Table 23. Doc ID 17713 Rev 1 L6460 Description ...

Page 67

... L6460 Table 23. Stepper sequencer direction StepDir 0 1 Note intended as clockwise the sequence that forces a clockwise rotation of the versors representing the current module and phase. Direction Counter clockwise (CCW) Clockwise (CW) Doc ID 17713 Rev 1 Power bridges 67/139 ...

Page 68

... I MAX . SENSE Doc ID 17713 Rev 1 L6460 MAX Max Unit - % of I MAX - % of I MAX - % of I MAX - % of I MAX - % of I MAX - % of I MAX - % of I MAX - % of I MAX - % of I MAX - % of I MAX ...

Page 69

... L6460 Table 25. Internal sequencer Full step Half (2 phases step on Control mode Full step 1/4 1/8 1/16 (1 phase step step step on Doc ID 17713 Rev 1 Power bridges Typical output current (% of IMAX) Phase A Phase B (sin) (cos) 1 70.7 70.7 2 77.3 63.4 3 83.1 55.6 4 88.2 47 ...

Page 70

... Doc ID 17713 Rev 1 L6460 Resulting Typical output electrical current (% of IMAX) angle Phase A Phase B Electrical (sin) (cos) degrees -63.4 -77.3 219.4° -70.7 -70.7 225° -77.3 -63.4 230.6° -83.1 -55.6 236.2° -88.2 -47.1 241.9° -92.4 -38.3 247.5° ...

Page 71

... L6460 Table 25. Internal sequencer (continued) Full step Half (2 phases step on) The voltage spikes on R the output of current sense comparator. The Blanking time selection is made by using the StepBlkTime[1:0] bits in the StpCfg1 register. The stepper driver off time could be programmed by means of the StepOffTime[4:0] bits in StpCfg1 register ...

Page 72

... Table 72/139 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 28. Doc ID 17713 Rev 1 Off time Unit Typ 42 µs 44 µs 46 µs 48 µs 50 µs 52 µs 54 µs 56 µs 58 µs 60 µs 62 µs 64 µs L6460 ...

Page 73

... L6460 Table 27. Stepper fast decay MixDecPhX[4:0] 14.1.6 Synchronous buck regulator configuration (Bridge 3) Bridge 3 can be configured to be used as 2 independent synchronous buck regulators single high current synchronous buck regulator using GPIOs pins in order to close the voltage loop. The resulting regulator(s) will implement a non linear, pulse skipping, control loop using an internally generated PWM signal ...

Page 74

... For detail about pulse skipping please refer to main switching regulator page 54. The output voltage will be externally set by a divider network connected on feedback pin. To reduce as much as possible the regulation voltage error L6460 has the possibility to switch between four regulator feedback voltage references (and consequence, four under- 74/139 V ...

Page 75

... Regulation loop As seen before L6460 contains 2 regulation loops for switching regulators that are used when bridge 3 is used as a regulator. These loops are assembled using internal comparators and filters similar to that used in main switching regulator. When bridge 3 is not used for this purpose or when only one regulation loop is needed, the control loop is available on a GPIO output thus enabling the customer to assembly a basic buck switching regulator using an external Power FET ...

Page 76

... The regulated output voltage will be externally set by a resistor divider network connected to V pin. L6460 has the possibility to choose between four voltage references (and REF_FB consequence, four under-voltage thresholds) using the serial interface. The feedback reference voltage selection is made by writing the SelFBRef[1:0] bits in the Aux3SwCfg1 register ...

Page 77

... L6460 the regulated current: the voltage provided at the I internal reference. L6460 has the possibility to choose between four voltage references using the serial interface, writing the SelCurrRef[1:0] bits in the Aux3SwCfg1 register. Regardless of the CurrRef voltage, if the I the internal current limitation will work (typical Ilimit current 4A). ...

Page 78

... When this control loop is intended to be used as a simple buck regulator, the proper Aux3BatteryCharge bit must be written in the Aux3SwCfg1 register. The regulator will also implement a soft start strategy. When L6460 “low power mode” is enabled this regulator will be disabled. Here after are summarized the primary features of the regulator: – ...

Page 79

... L6460 Table 29. Battery charger regulator controller PWM specification Aux3PWMTable [1: Typical duty cycle value 10% 13% 24% 61% Doc ID 17713 Rev 1 Power bridges Comments Default state 79/139 ...

Page 80

... ADC configuration register; no A/D conversion will be enabled if this register is not set from last power-up sequence. This ADC can be used to measure some external pins as well as some L6460’s internal voltages. The converter is based on a cyclic architecture with an internal sample-and-hold circuit. Sample time can be changed using serial interface to enable good measure of higher impedance sources ...

Page 81

... L6460 Figure 24. A2D block diagram V supply V pump V 3v3 V LINmain FB V SWmain FB V SWDRV_F B GPIO[0:14] RefOpAmpX OutStripStepperPHX Current DAC Temp Sensors Conversion Address 0 Conversion Address 1 The A2D system is enabled by setting the A2DEnable bit to ‘1’ in the A2DControl register. The A2DType bit in the A2DConfigX registers selects the A2D active configuration (8-bit resolution or 9-bit) according to the Table 30 ...

Page 82

... OutStripStepperPhA OutStripStepperPhB Not used ST reserved ST reserved ST reserved and Table 33. Doc ID 17713 Rev 1 L6460 Note See voltage divider specification. See voltage divider specification. Temperature sensor1 Temperature sensor2 See voltage divider specification. See current DAC circuit References AUX1 switching reg. 0.8V reference voltage ...

Page 83

... A2DConfigX register and a conversion on channel 2 can be triggered writing a logic ‘1’ in the A2DTrig2 bit in the same register. While a request on a channel is pending but not yet completed L6460 will force to logic ‘0’ the corresponding A2DdoneX bit in the A2DResultX registers and L6460 will not accept other conversion request on that channel. ...

Page 84

... Here below are reported the resistor voltage divider specifications: Table 34. Voltage divider specification Parameter R V Supply_ratio Supply R V SupplyInt_ratio Supply Int R V V3V3_ratio 3v3 84/139 Description divider ratio divider ratio divider ratio Doc ID 17713 Rev 1 Notes Min Typ Max - 1/15 - 1/15 - 1/2 L6460 Unit - - - ...

Page 85

... L6460 16 Current DAC circuit L6460 includes a multiple range 6-bit current sink DAC. The LSB value of this DAC can be selected using the DacRange[1:0] bits in the CurrDacCtrl register. The output of this circuit is connected to GPIO[8] that tolerant pin. The value of this pin can be converted using ADC. The pin value can be scaled before being converted by enabling the internal resistor divider connected to this pin ...

Page 86

... By changing LSB current value, all steps will change following this relation: where N is the value of DacValue[5:0] bits. 86/139 LSB typical current DacRange[0] I LSB 0 Disabled 1 10 µA 0 100 µ ( step LSB Doc ID 17713 Rev 1 L6460 Full scale typical typ current I typ FULL Disabled 0. ...

Page 87

... L6460 17 Operational amplifiers L6460 contains two rail to rail output, high bandwidth internally compensated operational amplifiers supplied by V Each operational amplifier can have all pin accessible or, to save pins, can be internally configured as a buffer. They can also be used as comparators that the user must disable internal compensation by writing a logic level “ ...

Page 88

... OP output current, and/or to add a low resistor (10 Ω) in series to the load capacitance. To use the operational amplifiers as comparators the user must disable internal compensation writing a logic one in the OpXDisComp bit in the OpAmpXCtrl register. 88/139 Doc ID 17713 Rev 1 L6460 ...

Page 89

... The turning on and off of each switch can be controlled through serial interface. L6460 provides 2 low voltage power switches, each of them has current limitation to minimum 150mA to limit inrush current when charging a capacitive load. When the limit current has been reached, for more than a T latched in the central logic and can be cleared by the firmware ...

Page 90

... General purpose PWM 19 General purpose PWM L6460 includes three general purpose PWM generators that can be redirected on GPIO pins (see Chapter a fixed period F OSC has a programmable base time clock and a programmable time for both high and low levels. 19.1 General purpose PWM generators 1 and 2 (AuxPwm1 and ...

Page 91

... L6460 20 Interrupt controller L6460 contains one programmable interrupt controller that can be used to advice the firmware, through the serial interface, when a certain event happens inside the IC. The output of the interrupt circuit can be also redirected on a GPIO pin therefore the event can be signaled directly to the external circuits. ...

Page 92

... The GPIO output of this circuit can be programmed to be active high or active low. 92/139 Event description Watch dog warning event Watch dog event Digital comparator ADC conversion done 1 ADC conversion done 2 AUX1 Ilimit event. Doc ID 17713 Rev 1 L6460 Notes (1) (1) ...

Page 93

... L6460 21 Digital comparator L6460 includes one digital comparator that can be used to signal, through serial interface, that a channel converted by the ADC is greater, greater-equal, lesser, lesser equal, or equal than a fixed value set by serial interface or than the value converted by the other ADC channel. This circuit can be used to monitor the temperature of the IC advising the firmware when it reaches a certain value decided by the firmware by setting one ADC channel to do continuous conversions of the temperature sensor ...

Page 94

... DigCmpSelCh0[1] Data0[9:0] COMPARATOR Data1 [9:0] DigCmpSelCh1[1] SelCmpType[1] SelCmpType[ DigCmpSelChX[ Doc ID 17713 Rev 1 L6460 ADC FSM Update Signal DigCmpUpdate[1:0] Three check s filter CmpOut Comparison type Disabled Data0[9:0] ≤1³1÷Data1[9:0] Data0[9:0] = Data1[9:0] Data0[9:0] > Data1[9:0] Data0[9:0] ≤= Data1[9:0] DataX[9:0] DigCmpValue[9:0] A2DResult1[8:0] A2DResult1[8:0] ...

Page 95

... L6460 22 GPIO pins Some of the pins of L6460 are indicated as GPIO (General purpose I/O). These pins can be configured to be used in different ways depending on customer application. All GPIOs can be used as digital input/output pins with digital value settable/readable using serial interface or as analog input pins that can be converted using the A2D system. Some of the pins can be used for special purposes: i ...

Page 96

... Open drain tolerant output Full driver connected to V GPIO_SPI Full driver connected to V GPIO_SPI Full driver connected to V GPIO_SPI Full driver BB (can be powered by V 3v3 metal change) Full driver connected to V GPIO_SPI Full driver connected to V GPIO_SPI L6460 Notes with a ...

Page 97

... This pin can be used as minus input for comparator 2. This pin can be used as feedback input for AUX1 regulator obtained by using bridge 3. This pin can be used to carry out the A2DGpo value related to the ADC L6460 conversion is doing. This pin can be used as output of the regulation loop used by AUX3 regulator obtained by using bridge 4 ...

Page 98

... Meaning This pin can be used as operational amplifier 2 output. This pin is used to determine the SPI ID1 bit value. This pin is used to determine the SPI ID2 bit value. This pin is used as slave control when the IC is configured as master. Doc ID 17713 Rev 1 L6460 ...

Page 99

... L6460 22.1 GPIO[0] The GPIO[0] truth table is (for the abbreviation list please refer to Table 41. GPIO[0] truth table State at GpioOut StartUp Enable [ all configurations in which GPIO[0] is enabled as output: a) the GPIO[0] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion ...

Page 100

... GPIO pins Figure 30. GPIO[0] block diagram From Serial Interface EnStartUpDtc From Power Up FSM 100/139 V To Serial Interface To ADC To Control Logic Start - up pin State Detect circuit V 3v3 Logic Decode Doc ID 17713 Rev 1 3v3 V 3v3 GPIO[0] V 3v3 GPIO[0] Driver L6460 ...

Page 101

... L6460 22.2 GPIO[1] The GPIO[1] truth table is (for the abbreviation list please refer to Table 42. GPIO[1] truth table AUX1Enable or GpioOut AUX1System Enable [ AUX1Enable or AUX1System bit =1 represent the case in which AUX1 is used as a system or not system regulator all configurations in which GPIO[1] is enabled as output: a) the GPIO[1] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion ...

Page 102

... GPIO pins Figure 31. GPIO[1] block diagram To AUX1 Feedback comparator From Serial Interface 102/139 V To Serial Interface To ADC V 3v3 Logic Decode Doc ID 17713 Rev 1 3v3 GPIO[1] V 3v3 Gpio[1] Driver L6460 ...

Page 103

... L6460 22.3 GPIO[2] The GPIO[2] truth table is (for the abbreviation list please refer to Table 43. GPIO[2] truth table AUX2Enable or GpioOut AUX2System Enable [ AUX2Enable or AUX2System bit =1 represent the case in which AUX1 is used as a System or Not System regulator all configurations in which GPIO[2] is enabled as output: a) the GPIO[2] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion ...

Page 104

... GPIO pins Figure 32. GPIO[2] block diagram To AUX2 Feedback comparator From Serial Interface 104/139 To ExtPWM3 To Serial Interface To ADC V 3v3 Logic Decode Doc ID 17713 Rev 1 V 3v3 GPIO[2] V 3v3 Gpio[2] Driver L6460 ...

Page 105

... L6460 22.4 GPIO[3] The GPIO[3] truth table is (for the abbreviation list please refer to Table 44. GPIO[3] truth table State at GpioOut StartUp Enable [ all configurations in which GPIO[3] is enabled as output: a) the GPIO[3] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion ...

Page 106

... GPIO pins Figure 33. GPIO[3] block diagram To Control Logic From Serial Interface EnStartUpDtc From Power Up FSM 106/139 To Serial Interface To ADC Start - up pin State Detect circuit V 3v3 Logic Decode Doc ID 17713 Rev 1 V 3v3 V 3v3 GPIO[3] V 3v3 Gpio[3] Driver L6460 ...

Page 107

... L6460 22.5 GPIO[4] The GPIO[4] truth table is (for the abbreviation list please refer to Table 45. GPIO[4] truth table State at GpioOut StartUp Enable [ all configurations in which GPIO[4] is enabled as output: a) the GPIO[4] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion ...

Page 108

... GPIO pins Figure 34. GPIO[4] block diagram To Control Logic From Serial Interface EnStartUpDtc From Power Up FSM 108/139 To Serial Interface To ADC Start - up pin State Detect circuit V 3v3 Logic Decode Doc ID 17713 Rev 1 V 3v3 V 3v3 GPIO[4] V 3v3 Gpio[4] Driver L6460 ...

Page 109

... L6460 is used as a master device Doc ID 17713 Rev 1 GPIO pins Table 40). Function Note X Slave control (3) X Reg Loop1 OUT X HiZ (SPI_IN) (3) 0 SPI OUT (3) 1 Comp1OUT (3) 0 Reg Loop1 OUT (3) 1 AuxPwm3 (3) 0 SPI OUT inverted (3) 1 Comp1OUT inverted Reg Loop1 OUT ...

Page 110

... GPIO pins Figure 35. GPIO[5] block diagram To internal Logic & SPI To ADC From Control logic 110/139 V 3v3 V 3V3 V 3v3 Logic Decode Doc ID 17713 Rev 1 L6460 GPIO[5] Back to Back Driver ...

Page 111

... L6460 22.7 GPIO[6] The GPIO[6] truth table is (for the abbreviation list please refer to Table 47. GPIO[6] truth table AEnLow StdByMode VSw[ When EnLowVSw[1]= ‘1’ the GpioOutEnable[6] bit is forced all configurations in which GPIO[6] is enabled as output: a) the GPIO[6] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion ...

Page 112

... GPIO pins Figure 36. GPIO[6] block diagram To internal Logic & SPI Stand By mode 112/139 V GPIO_SPI Power Switch 1 To ADC V 3v3 From Serial Interface Logic Decode Doc ID 17713 Rev 1 V 3v3 V 3v3 GPIO[6] Gpio[6] Driver L6460 ...

Page 113

... L6460 22.8 GPIO[7] The GPIO[7] truth table is (for the abbreviation list please refer to Table 48. GPIO[7] truth table EnLowVSw[ When EnLowVSw[2] = ‘1’ the GpioOutEnable[7] bit is forced all configurations in which GPIO[7] is enabled as output: a) the GPIO[7] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion ...

Page 114

... GPIO pins Figure 37. GPIO[7] block diagram To internal Logic & SPI From Serial Interface 114/139 V GPIO_SPI Power Switch 2 To ADC V V 3v3 Logic Decode Doc ID 17713 Rev 1 V 3v3 GPIO_SPI GPIO[7] L6460 ...

Page 115

... L6460 22.9 GPIO[8] The GPIO[8] truth table is (for the abbreviation list please refer to Table 49. GPIO[8] truth table (1) EnDac The EnDAC bit in the CurrDacCtrl register enables the Current DAC 2. This pin is 5 volt input tolerant. 3. When EnDAC = ‘1’ the GpioOutEnable[8] bit is forced to 0. The current DAC circuit is directly connected to GPIO[8] pin so as soon enabled it will sink current from pin ...

Page 116

... GPIO pins Figure 38. GPIO[8] block diagram EnGpio8 DigIn To ADC V From Serial Interface 116/139 V To internal Logic & SPI V 3v3 Logic Decode Gpio[8] Driver From Serial Current Sink Circuit Interface Doc ID 17713 Rev 1 3v3 3v3 L6460 GPIO[8] ...

Page 117

... L6460 22.10 GPIO[9] The GPIO[9] truth table is (for the abbreviation list please refer to Table 50. GPIO[9] truth table (1) Op1EnPlusPin The Op1EnPlusPin bit in the OpAmp1Ctrl register enables the connection of the positive input of Op1 to GPIO[9] pin. 2. The GPIO[9] pin is used by the system when firmware requires the ID read action 3. When Op1EnPlusPin = ‘ ...

Page 118

... GPIO pins Figure 39. GPIO[9] block diagram ID1 SampleID To ADC From SPI To OpAmp1 In+ 118/139 V 3v3 To internal Logic & SPI Pin State Sample Circuit V GPIO_SPI V 3v3 Logic Decode Doc ID 17713 Rev 1 Gpio[9] Driver L6460 GPIO[9] ...

Page 119

... L6460 22.11 GPIO[10] The GPIO[10] truth table is (for the abbreviation list please refer to Table 51. GPIO[10] truth table (1) Op1EnPlusPin The Op1EnMinusPin bit in the OpAmp1Ctrl register enables the connection of the positive input of Op1 to GPIO[10] pin. 2. The GPIO[10] pin is used by the system when firmware requires the ID read action 3. When Op1EnPlusPin = ‘ ...

Page 120

... GPIO pins Figure 40. GPIO[10] block diagram ID2 SampleID To ADC From SPI To OpAmp1 In - 120/139 V 3v3 To internal Logic & SPI Pin State Sample Circuit V GPIO_SPI V 3v3 Logic Decode Doc ID 17713 Rev 1 Gpio[10] Driver L6460 GPIO[10] ...

Page 121

... L6460 22.12 GPIO[11] The GPIO[11] truth table is (for the abbreviation list please refer to Table 52. GPIO[11] truth table (1) EnOpl The EnOp1 bit in the OpAmp1Ctrl register enables the operational amplifier 1. 2. When EnOp1 = ‘1’ the GpioOutEnable[11] bit is forced all configurations in which GPIO[11] is enabled as output: a) the GPIO[11] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion ...

Page 122

... GPIO pins Figure 41. GPIO[11] block diagram To ADC From Central Logic 122/139 V 3v3 To internal Logic & SPI V GPIO_SPI V 3v3 Logic Decode OpAmp 1 Doc ID 17713 Rev 1 L6460 GPIO[11] ...

Page 123

... L6460 22.13 GPIO[12] The GPIO[12] truth table is (for the abbreviation list please refer to Table 53. GPIO[12] truth table AUX2enable Op2En or PlusPin AUX2syste ( AUX2Enable or AUX2System bit =1 represent the case in which AUX2 is used as a regulator (system or not system). 2. When Op2EnPlusPin = ‘1’ the GpioOutEnable[11] bit is forced to 0. ...

Page 124

... GPIO pins Figure 42. GPIO[12] block diagram To ADC From SPI To OpAmp2 In+ 124/139 V 3v3 To internal Logic & SPI V GPIO_SPI V 3v3 Logic Decode Back to Back Doc ID 17713 Rev 1 Driver L6460 GPIO[12] ...

Page 125

... L6460 22.14 GPIO[13] The GPIO[13] truth table is (for the abbreviation list please refer to Table 54. GPIO[13] truth table Op2En (1) mimusPin The Op2EnMinusPin bit in the OpAmp2Ctrl register enables the connection of the positive input of Op1 to GPIO[13] pin. 2. When Op2EnMinusPin = ‘1’ the GpioOutEnable[13] bit is forced to 0. ...

Page 126

... GPIO pins Figure 43. GPIO[13] block diagram To ADC V From SPI To OpAmp2 In - 126/139 V 3v3 To internal Logic & SPI V GPIO_SP 3v3 Logic Decode Doc ID 17713 Rev 1 GPIO[13] Gpio[13] Driver L6460 ...

Page 127

... L6460 22.15 GPIO[14] The GPIO[14] truth table is (for the abbreviation list please refer to Table 55. GPIO[14] truth table (1) EnOp2 GpioOut enable[14 The EnOp2 bit in the OpAmp2Ctrl register enables the operational amplifier 2. 2. When EnOp2 = ‘1’ the GpioOutEnable[14] bit is forced all configurations in which GPIO[14] is enabled as output: a) the GPIO[14] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion ...

Page 128

... GPIO pins Figure 44. GPIO[14] block diagram To ADC From Central Logic 128/139 V 3v3 To internal Logic & SPI V GPIO_SP V 3v3 Logic Decode OpAmp 2 Doc ID 17713 Rev 1 Gpio[14] Driver L6460 GPIO[14] ...

Page 129

... Slave devices do not respond to transactions unless their nSS input signal is driven low. Master device interfacing with multiple SPI slave devices has an nSS signal for each slave device. L6460 will maintain its MISO pin in high impedance until it does not recognize its address in serial frame. 23.1 ...

Page 130

... L6460 IC address; 4. 1-bit reserved for future use that must be set at “0”. The data to be written (MSB first D15…D0) are then read from MOSI pin. The length of data field can bits, but only the first 16-bit are accepted as valid data ...

Page 131

... L6460 Figure 47. SPI input timing diagram T nss setup nSS SCLK MOSI T mosi setup Figure 48. SPI output timing diagram T nss setup nSS SCLK MOSI MISO mosi hold T sclk rise miso valid Doc ID 17713 Rev 1 Serial interface sclk period nss hold nss min ...

Page 132

... Registers list 24 Registers list Many of the L6460 functionalities are controlled or can be supervised by accessing to the relative register through serial interface. All these registers can be seen from the user (microcontroller) point of view as a register table. Each register is one word wide (16-bit) and can be read using a 7-bit address Table 56 ...

Page 133

... L6460 Table 56. Register address map (continued) Address[6:0] (binary) 001_1100 001_1101 001_1110 001_1111 010_0000 010_0001 010_0010 010_0011 010_0100 010_0101 010_0110 010_0111 010_1000 010_1001 010_1010 010_1011 010_1100 010_1101 010_1110 010_1111 011_0000 011_0001 011_0010 011_0011 011_0100 011_0101 011_0110 011_0111 011_1000 011_1001 011_1010 011_1011 011_1100 ...

Page 134

... Registers list Table 56. Register address map (continued) Address[6:0] (binary) 011_1101 011_1110 011_1111 134/139 Address[6:0] Name Comment (binary) 111_1101 111_1110 111_1111 Doc ID 17713 Rev 1 L6460 Name Comment RESERVED RESERVED RESERVED ...

Page 135

... L6460 25 Schematic examples Figure 49. Application with 2 DC motors, 1 stepper motor and 3 power supplies 3 2 DC1_plus DC3_sense 1 48 Gpio5 VSWDRV_sns 2 47 Gpio9 VSWDRV_FB 3 46 Gpio10 Gpio4 Gpio4 4 45 Gpio11 Gpio3 Gpio3 5 44 N.C. DC1_minus 6 43 DC1_minus DC3_minus 7 42 GND1 DC3_sense 8 41 DC4_sense ...

Page 136

... DC1_minus N.C. 6 DC1_minus DC3_minus 7 GND1 DC3_sense 8 GND2 DC4_sense 9 DC2_minus DC4_minus 10 N.C. DC2_minus 11 Gpio2 Gpio14 Gpio2 12 Gpio1 Gpio13 Gpio1 13 Gpio0 Gpio12 Gpio0 14 nSS nAWAKE nSS 15 DC2_plus DC4_sense 16 TAB 70 TAB 71 TAB 72 TAB Doc ID 17713 Rev Gpio5 46 Gpio9 45 Gpio10 44 Gpio11 Gpio14 36 Gpio13 35 Gpio12 L6460 ...

Page 137

... L6460 26 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: ECOPACK trademark. Figure 51. TQFP64 mechanical data an package dimensions DIM. MIN. ...

Page 138

... Revision history 27 Revision history Table 57. Document revision history Date 02-Jul-2010 138/139 Revision 1 Initial release. Doc ID 17713 Rev 1 L6460 Changes ...

Page 139

... L6460 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...